Abstract: Provided is a method of removing noise from digital moving picture data reducing the number of frames used in a temporal filtering operation and able to detect motion between frames easily. The method comprises a method of spatial filtering, a method of temporal filtering, and a method of performing the spatial filtering and the temporal filtering sequentially. The spatial filtering method applies a spatial filtering in a YCbCr color space, preserving a contour/edge in the image in the spatial domain, and generating a weight that is adaptive to the noise for discriminating the contour/edge in the temporal filtering operation.

Abstract: A fractional-N frequency synthesizer supporting multi-band operation, having variable frequency resolution obtained by sigma-delta modulating a multi-bit frequency resolution control signal having at least one pulse, the at least one pulse having a period of P and a variable duty cycle. Frequency resolution can be increased by changing the duty cycle and without increasing input bits to the sigma-delta modulator. Thus, a core size of the sigma-delta modulator may be reduced.

Abstract: A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.

Abstract: A semiconductor memory device includes a control signal generator for combining command signals applied from an external portion to generate a test signal; a set/reset signal generator for receiving a mode setting signal applied from an external portion in response to the test signal and generating a first set/reset signal when the mode setting signal is a signal that designates an individual set/reset; a test logic portion for storing and then outputting the mode setting signal in response to the test signal; a set/reset master signal generator for receiving the first set/reset signal to output a set/reset master signal for commonly controlling a test mode of internal blocks of the semiconductor memory device; and a test control signal generator for combining an output signal of the test logic portion to generate a plurality of control signals and generating the set/reset master signal as a plurality of test control signals in response to the plurality of control signals.

Abstract: A method of detecting errors in a priority encoder and a content addressable memory (CAM) adopting the same are provided. The CAM includes a CAM cell array, a priority encoder, and a shift register unit. The priority encoder tests the CAM cell array to determine if the CAM cell array has errors by comparing search data with data stored in the CAM cell array. The shift register unit, in response to a clock signal, transmits first through mth test data to the priority encoder to test the priority encoder. Then, the logic levels of the first through mth test data are sequentially changed in synchronization with the clock signal. If there are no errors in the priority encoder, the priority encoder sequentially outputs word line addresses of a most significant bit through a least significant bit of the CAM cell array.

Abstract: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

Abstract: The present invention is broadly directed towards a receiving container for an LCD apparatus for securing a lamp and lamp wiring connected to a lamp. The receiving container has features for substantially preventing the lamp wiring from being disconnected from the lamp. For example, a first through-hole for receiving the lamp wiring, a first trench, securing members, and securing projections are utilized to substantially prevent lamp wiring from being disconnected from a lamp. Additionally, the LCD apparatus is easily handled, dissipates heat effectively, and has a light weight.

Abstract: A voltage conversion circuit changes an input signal of a first voltage into an output signal of a second voltage. The circuit includes an input terminal receiving an input signal, an output terminal generating an output signal, and first and second level-shifting units connected in parallel between the input and output terminals. The first and second level-shifting units have different transition delay characteristics, enabling rising and falling transition delays to be variable in the same ratio when the first and second voltages are changed.

Abstract: A digital-to-analog converter using capacitors and an operational amplifier, which can be highly integrated due to its small area and which can rapidly perform a stable converting operation. The digital-to-analog converter includes a data input unit, a first conversion unit, a second conversion unit, and a signal output unit. When digital data is input to the data input unit, the data input unit is connected to the first conversion unit or the second conversion unit. The first conversion unit charges a first charging capacitor with a voltage corresponding to the input digital data and distributes the charged charges to a first distribution capacitor. The second conversion unit charges a second charging capacitor with the voltage corresponding to the input digital data and distributes the charged charges to a second distribution capacitor.

Abstract: An entertainment system comprises a media source, and a housing for supporting the media source, wherein the housing is coupled to an inner portion of a seat of a vehicle, and the media source is capable of being selectively connected to and disconnected from the housing.

Abstract: A method of manufacturing a thin film transistor (TFT) substrate to minimize a rugged surface of an organic layer overlapping with a storage electrode is provided. The method includes forming a passivation layer on a substrate having a storage electrode and an organic layer covering the passivation layer, forming a concave portion by partially removing a portion of the organic layer that overlaps with the storage electrode, planarizing a rugged pattern located on the bottom of the concave portion, and forming an opening extending to a surface of the passivation layer by removing the planarized organic layer from the concave portion.

Abstract: A voltage generation circuit and semiconductor memory device including the same are provided.

Abstract: An IC card system for transceiving data signal between an IC card processor and an IC card in the manner of non-contact are provided. The IC card modulates the signal to be transmitted to the processor in the manner of Quadrature Amplitude Modulation and generates the modulated signal. A card reader demodulates the signal received from the IC card in the manner of QAM. The rate of the data signal transmitted from the IC card to the card reader is improved.

Abstract: A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

Abstract: Provided are a TFT-LCD source driver employing a frame cancellation and half decoding method, and a source line driving method. The TFT-LCD source driver outputs source line driving voltages for every two channels among a plurality of channels. Positive first and second gray scale voltages generated by a positive half decoder and negative first and second gray scale voltages generated by a negative half decoder are selectively transmitted to first and second output buffers through a chopping multiplexer in response to a chopping control signal. Output signals of the first and second output buffers are output to first and second channels through a polarity multiplexer in response to a polarity control signal.

Abstract: An optical disc system and a method of managing shock while recording or playing data in the optical disc system are provided. The optical disc system includes an optical pick-up unit for applying a laser beam to a track of an optical disc and detecting reflected light, a servo unit for controlling tracking and focus of the optical pick-up unit and a monitoring unit for comparing a monitoring signal, which is output from the optical pick-up unit and the servo unit, with a reference signal and generating a blocking signal and a blocking release signal. Recording or playing of data on the optical disc is stopped in response to the blocking signal, and recording or playing of the data on the optical disc is resumed in response to the blocking release signal based on a state of the optical disc system when recording or playing was stopped.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover a transfer gate and a floating diffusion layer. Therefore, the floating diffusion layer may not be attacked by an etching during a formation of sidewall spacers of various gates or by ion implantation during a formation of a junction region of a DDD or LDD structure, thus reducing a leakage current and a dark current at the floating diffusion layer.

Abstract: Cryptographic systems and methods that support multiple modes of operation, such as CBC, CTR and/or CCM modes. In one aspect, a method for encrypting data includes reading a plaintext data block from a memory, storing the plaintext data block in an input buffer, encrypting the plaintext data block in the input buffer using a first mode to generate a first ciphertext, storing the first ciphertext in an output buffer, encrypting the plaintext data block in the input buffer using a second mode to generate a second ciphertext. For example, in a CCM mode of operation wherein the first mode is a CTR (counter) mode and the second mode is a CBC (cipher block chaining) mode, the block of plaintext that is initially read from memory and stored in the data input register is applied to both the CTR and CBC modes, thereby reducing a number memory read operations as in conventional CCM modes.

Abstract: A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.