Abstract: Provided is a low power random bit generator utilizing a multiplying digital to analog converter (MDAC) which is used in a switched capacitor amplifying circuit and an analog to digital converter with a pipeline architecture. The low power random bit generator includes: an MDAC, outputting a predetermined analog voltage formed by using a ground voltage, a reference voltage, an initial voltage and a digital signal; a comparator, outputting a direct current (DC) voltage determined by comparing the analog voltage with the ground voltage; and a data storage unit, storing a predetermined digital signal corresponding to the DC voltage, and outputting the digital signal.

Abstract: A capacitor has a lower electrode formed on an insulation layer, a dielectric layer formed on the lower electrode, an upper electrode layer formed on the dielectric layer, and a first protection layer pattern formed on the upper electrode layer. The upper electrode layer is etched using the first protection layer pattern to form an upper electrode. A second protection layer is formed enclosing the dielectric layer, the upper electrode and the first protection layer pattern.

Abstract: There is provided a resistor-capacitor (RC) oscillator circuit insensitive to process, voltage, and temperature variances. The RC oscillator circuit includes a delay unit, a resistor unit, a capacitor, a resistor, and a first controller. The delay unit delays and outputs a signal received through an input terminal. The resistor unit is connected between an input terminal of the delay unit and a first node. The capacitor is connected between an output terminal of the delay unit and the first node. The resistor is connected between the input terminal of the delay unit and an output node. The first controller is connected between the output terminal of the delay unit and the output node, wherein a frequency signal is output through the output node.

Abstract: An operational amplifier includes: a differential amplifier for differentially amplifying first and second differential input signals to generate first and second output signals through first and second nodes; a driver for driving an output node in response to the second output signal; and a drive current adjuster for adjusting a driving current of the driver in response to the first output signal.

Abstract: An internal voltage converter and method is provided capable of reducing power consumption using a selective voltage reference, a semiconductor device including the internal voltage converter. A semiconductor device uses the internal voltage converter which discriminates an IVC stand-by state from a normal operation state, selects a voltage reference with low power consumption among selective voltage references in the IVC stand-by state, and generates an internal voltage.

Abstract: A phase change memory device for use in a burst read operation and a data reading method are provided. The memory device includes a plurality of bit lines and a plurality of word lines. A memory cell array block has a plurality of phase change memory cells that are connected to cross points of the plurality of bit lines and the plurality of word lines. A sense amplifier block is connected to corresponding bit lines, and latches data of memory cells connected to the same word line simultaneously during a burst read operation, and then provides the latched data in response to a column address.

Abstract: The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof.

Abstract: A liquid crystal display (LCD) is provided, which includes: first and second gate lines, a data line intersecting the gate lines, first to fourth drain electrodes located near the intersections between the first and second gate lines and the data line, and a coupling electrode. First to fourth pixel electrodes respectively connected to the first to fourth drain electrodes are also provided, and the first pixel electrode is connected to the coupling electrode while the fourth pixel electrode overlaps the coupling electrode. The LCD further includes a common electrode opposite the pixel electrodes, a liquid crystal layer interposed between the pixel electrodes and the common electrode, and a domain partitioning member formed on at least one of the pixel lelectrode and the common electrode. Two long edges of the domains are angled with respect to the first and the second gate lines or the data line substantially by about 45°.

Abstract: A content addressable memory (CAM) device is provided that includes a primary cell array having at least one entry in which a plurality of CAM cells are connected to word lines and match lines, a redundant cell array having entries formed in the same structure as that of the entries in the primary cell array to substitute for a defective entry including one or more defective CAM cells in the primary cell array, an encoder for receiving a match signal from an entry in the CAM array block having data matching search data to generate final entry information, and an entry controlling circuit for determining whether each entry in the CAM array block is used to generate the final entry information at the encoder, and inhibiting a signal applied from a match line of the defective entry from participating in generating the final entry information at the encoder.

Abstract: A liquid crystal display having electrodes on a single substrate includes a transparent planar electrode elongated in the transverse direction formed on the inner surface of the substrate, and an insulating film is deposited thereon. A plurality of linear electrodes, which are elongated in the longitudinal direction and either transparent or opaque, are formed on the insulating film. When voltages applied, the electric field is symmetrical with respect to the longitudinal central line of the linear electrodes and the longitudinal central line of a region between the linear electrodes, and has parabolic or semi-elliptical lines of force having a center on a boundary line between the planar and the linear electrodes.

Abstract: In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads.

Abstract: A flash cell fuse circuit includes a fuse cell array, a plurality of switch circuits and a plurality of fuse sense amplifiers. The fuse cell array outputs first signals in response to word line enable signals after a program or erase operation. The switch circuits pass one of the first signals in response to a reset signal and one of the word line enable signals. The fuse sense amplifiers each generate a fuse signal by detecting and amplifying an output signal of a corresponding switch circuit.

Abstract: Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to a first input signal, and the second signal response unit responds to a second input signal. The current source unit has a plurality of bias unit pairs for restricting currents provided to the first and second signal response units to respective source currents thereof. The bias unit pairs each include at least two bias units, which are separately arranged on opposite sides of a predetermined imaginary centerline. According to the layout structure of the signal driver of the present invention, there is a benefit in that current mismatch occurring between the first and second current response units is reduced, thus consequently improving the operating characteristics of the signal driver.

Abstract: An apparatus for testing electrical characteristics of a semiconductor workpiece includes a probe card having probes and signal pads electrically connected to the probes, wherein the probes are in contact with a workpiece during a test process; a test head electrically connected with a performance board having signal pads; and a pogo module having pogo pins for electrically connecting the signal pads of the probe card with the signal pads of the performance board during a test process, wherein at least two the pogo pins are electrically connected in parallel to one of the signal pads of the probe card, and wherein at least two pogo pins are electrically connected in parallel to one of the signal pads of the performance board. A resistance caused by the pogo pins is lowered to test the electrical characteristics of a semiconductor workpiece more precisely and a test process is performed even when one of the pogo pins is in poor contact with a pad.

Abstract: Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically adsorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically adsorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically adsorb the second reactant onto the substrate.

Abstract: A delay control circuit capable of controlling a delay time is disclosed. The delay control circuit includes a delay detecting circuit, a first pulse generator, a counter control circuit and a counter. The delay detecting circuit delays an input signal by a first time in response to an output signal and compares the input signal and the delayed input signal to generate a first signal. The first pulse generator generates a second signal in response to the input signal. The counter control circuit generates a count-up signal and a count-down signal in response to the first signal and the second signal. The counter generates the output signal in response to the count-up signal and the count-down signal to divide the first time by 2n intervals, wherein n is a positive integer.

Abstract: An amplifier capable of controlling the magnitudes of quiescent and output current, using externally supplied voltages. The amplifier includes: an input circuit converting a voltage difference between input signals into a current; an output circuit outputting an output current to the outside of the (class AB) amplifier (in response to a change in voltages at the first and second output nodes of the input circuit); a first control circuit generating a first bias current (when a first control voltage is applied), and a first control current; and a second control circuit generating a second bias current (whose magnitude is less than that of the first bias current) when a second control voltage is applied, and a second control current. In a first operating mode the first bias current controls the magnitude of quiescent flowing through the output circuit. The first control circuit and the output circuit form a current mirror.

Abstract: A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes; and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, form

Abstract: A method and apparatus for controlling a device by a serial link from a dual processor system. The configuration of the circuit is simplified and efficiency is enhanced by using independent internal buses and serial link control hardware for each processor and by selecting the active control hardware through arbitration. An MCU and a DSP can operate asynchronously and use their respective internal bus at the same time.

Abstract: An input buffer circuit achieving rail-to-rail operation maintains a uniform common mode output voltage even though an input signal having any voltage level is inputted. The input buffer circuit has a differential amplifier structure receiving two differential input signals. A first input part has a first inverter circuit into which a first differential input signal is inputted, and a second input part has a second inverter circuit into which the second differential input signal is inputted. The first inverter circuit has a first output node connected to a diode structure having an operating current twice the operating current of the first inverter circuit, and outputs a first output signal. Rail-to-rail operation is achieved, and a common mode output voltage is provided uniformly, with reduced current consumption.