Abstract: A filter circuit with two 2nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is implemented with a low Q factor and an imaginary zero. The first stage is designed to further eliminate the unwanted frequency components. The imaginary zero in the second stage eliminates the noise present in the output of the first stage due to the requirement of high Q in the first stage. Any additional noise introduced by the second stage is minimal due to the low Q of the second stage. Each stage may be implemented using only a single operational amplifier when the first stage generates a differential output signal.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: The objective of the invention is to provide a booster circuit with reduced power consumption and switching noise. Booster circuit 1 of the present invention has gate circuits 41-47 an auxiliary control circuit 9. Each of gate circuits 41-47 has charging/discharging circuit 11 and auxiliary charging/discharging circuit 12 used for charging/discharging capacitors 51-57. Under the control of auxiliary control circuit 9, said charging/discharging circuit 11 can operate independently or operate together with auxiliary charging/discharging circuit 12. When the booster circuit is started, charging/discharging circuit 11 and auxiliary charging/discharging circuit 12 are operated together to increase the drivability of gate circuits 4. As a result, the charging time of capacitors 51-57 in charge-pump circuits 21-27 can be shortened. On the other hand, at steady state, charging/discharging circuit 11 operates independently.

Abstract: A method of testing integrated circuits for the effect of NBTI degradation. A static DC stress voltage is applied to the voltage supply input of the circuit. This circuit is held at this voltage for a given stress period. The application of the DC voltage is equivalent to applying a negative gate bias, and isolates the effects of NBTI degradation from CHC (channel hot carrier) degradation or other degradation that occurs when the circuit has a clocked input.

Abstract: A new heat sink apparatus and method that simplify the assembly of the heat sink and thermal stud. The new heat sink assembly uses a spring retainer that, in most cases, can use existing socket mounting screws. A spring clip presses a thermal stud against the back of an electrical device package. The present invention is especially useful for attaching a spatial light modulator to a printed circuit board since it provides a simple, reliable heat sink without blocking the light path to and from the device.

Abstract: A monitoring system (10) includes a video camera (12) which generates images of a monitored area. A computer (16) receives the images from the video camera, and contains a digitized map (85) of the monitored area. One of the detected images (84) is saved as a reference image. An operator defines a first region (86) corresponding to a selected portion of the monitored area, as viewed in the reference image, and defines a second region (87) which corresponds to the selected portion of the area as viewed on the map. Subsequent images from the camera are compared to the reference image, in order to identify an object of interest, and a first point associated with the object is identified. If the first point is within the first region, a warp transformation of the first point from the first region to the second region is carried out, in order to identify within the second region a second point which corresponds to the first point, and which identifies the location on the map of the object of interest.

Abstract: An optical switch ideally suited for use as an optical add drop multiplexer (OADM). A light beam entering the OADM through a first input fiber (402) is separated by wavelength to yield multiple light beams (902, 904). One light beam (902) is reflected by one or more of the mirrors in mirror array (908). Depending on the position of the mirrors struck by light beam (902), the beam is reflected to a first region of a retro-reflector (910) or a second region (912). When light beam (902) is reflected by the second region (912) of the retro-reflector, it again travels to the mirror array (908) and is then reflected to a wavelength combiner (914) and output on the second (“drop”) output fiber (408). While a first wavelength light beam (902) is reflected to the drop output (408), other wavelengths of light from the first input (402), for example light beam (904), are directed to the “out” optical fiber (406).

Abstract: A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size, a source increment size, a target word size and a target increment size. A byte shifter/register that will shifts a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.

Abstract: A multi-mode color filter 400 having an inner hub region 402 used to mount the color filter 400 to a motor shaft. A first track 404 and a second track 406 of color filter segments arc formed on the color filter, as is an optional clear track 406. The first and second tracks each have a different set of color filters. One set of filters is chosen to improve image brightness, another set is selected to improve color saturation. Typically, the set of filters used to improve brightness includes one or more clear segments, while the set of filters selected to improve color saturation does not. Depending on the image being projected, the user or the display controller moves the color wheel to select a particular filter set.

Abstract: Apparatus and methods are disclosed for electroplating conductive films on semiconductor wafers, wherein field adjustment apparatus is located in a reservoir between a cathode and an anode to influence the electric field used in the plating process. Field adjustment apparatus is presented having one or more apertures, which may be selectively plugged to adjust the electrical fields during plating.

Abstract: A method for evaluating a mask pattern for a product that is manufactured by a process that is described at least in part by a mathematical process model includes the steps of: (a) selecting a reference locus; (b) determining a sampling direction from the reference locus; (c) selecting a sampling locus in the sampling direction; (d) evaluating a model factor at the sampling locus; and (e) applying at least one predetermined criterion to the model factor to determine a conclusion. If the conclusion is a first inference, (f) repeating steps (c) through (e). If the conclusion is a second inference, (g) determining whether the evaluation is complete and repeating steps (a) through (g) until the evaluating is complete.

Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

Abstract: The present invention provides a system and method for evaluating gate oxide integrity in a semiconductor wafer. The system may include: a semiconductor wafer; a layer of gate oxide on the semiconductor wafer; a layer of polysilicon on the gate oxide; an electron beam microscope with adjustable energy levels, wherein the electron beam is directed at the semiconductor wafer; an electron beam inspection tool used to detect passive voltage contrasts within the gate oxide layer. The system may also include a measuring tool for measuring an electrical current level of the semiconductor substrate. The system may also include an electrical ground connected to the semiconductor wafer. The system may also include the energy levels vary from about 600 eV to 5000 eV.

Abstract: A low drop-out voltage regulator circuit includes: a MOS pass through transistor 12; a resistor feedback circuit 18 and 20 coupled to the MOS pass through transistor 12; an amplifier 16 having an input coupled to the resistor feedback circuit 18 and 20; a Class A output stage 22 coupled between an output of the amplifier 16 and a gate of the MOS pass through transistor 12; and a speedup circuit 48 coupled between the output of the amplifier and the gate of the MOS pass through transistor.

Abstract: A switch mode converter uses the bootstrap capacitor 30 to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry. The additional circuitry includes a charge pump 40 and a duty cycle detect device 42. When the duty cycle detect device 42 detects that the converter is attempting to operate in 100% duty cycle, the charge pump 40 provides additional charge to the bootstrap capacitor 30 to ensure that the 100% duty cycle is maintained.

Abstract: External output terminal 28 is clamped by clamping circuit 20, and a current mirror is configured using diode circuit 23 within clamping circuit 20 and detector transistor 34. When the voltage of external output terminal 28 can no longer be maintained by the first current supply circuit 11 alone as load 27 increases, clamping circuit 20 shuts off, and detector transistor 34 shuts off. As detector transistor 34 shuts off, the second current supplying element 12 becomes conductive and supplies a current to load 27. Because the second current supplying element 12 is not operating during normal operation during which the current consumption by load 27 is low, the current consumption is low. In addition, because no amplifier is required, only a small number of elements are required.

Abstract: A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor wafer in proximity to the reticle; directing radiation through a first plurality of the pixels onto a first location on the wafer; changing the relative positions of the semiconductor wafer and the reticle; and directing radiation through a second plurality of the pixels onto a second location on the wafer. The first plurality of pixels can be used to form a first mark and the second plurality of pixels can be used to form a second mark, wherein the second mark is different from the first mark. The marks can be made of a pattern of dots in order to save space. The pixels can be selected to form certain marks by using a computer 304 to turn on or off a transistor that may be associated with each pixel. Also described is a system for marking a semiconductor wafer.

Abstract: A circuit for power amplification for an audio amplifier that reduces power supply noise amplified to the load. The circuit takes the prior art circuit's existing output coupling cap and power supply decoupling cap and connecting them in series from the power supply to ground. The output of the amplifier is then directly coupled to the load and the other side of the load is connected at the “null point” between the two capacitors.

Abstract: Disclosed is apparatus and method for establishing and maintaining optical data transfer between a first optical communications device (202) and a second optical communications device (204). The devices have a feedback communications link (216) therebetween. An optical signal (214), having a predetermined signal profile (306), is transmitted from a transmission source (104) within the first optical communications device to an optical receiver (112) within the second optical communications device. The predetermined signal profile is transmitted from the first device, via the feedback communications link, to the second device. The signal profile (408) of the optical signal as received by the optical receiver is determined, and compared with the predetermined signal profile to quantify any misalignment or movement of the optical signal with respect to the optical receiver.

Abstract: A phase lock loop to control phase error including a first phase error detector to detect the phase error in a first mode, a first loop filter to filter a first phase error by using a first factor, a second phase error detector to detect a second phase error in a second mode, a second loop filter to filter a second phase error by using a second factor, and a circuit to select either the first phase error or the second phase error in accordance with the first or second mode.