Abstract: A digital transformation system for converting between logarithm functions and floating point functions very quickly by normalizing the floating point number in the range of one to two, and adapting one function as the other function, after a correction, which correction is generated by a ROM using the one function as an address.

Abstract: A circuit for regulating the internal programming voltage (Vpp) supplied to an integrated circuit memory device. The invention limits the internal programming voltage to a maximum value no greater than the field assisted breakdown voltage of on-chip transistors and/or the field transistor threshold voltage. Representatives of the several different types of transistors provided on an integrated circuit substrate are incorporated into the voltage regulating circuit. The regulator transistors are placed in the circuit in such a way that they are designed to break down first in the event of an excessive internal programming voltage (Vpp). In this way, the regulator transistors limit the voltage sent to the operating circuitry of the integrated circuit.

Abstract: Reduction of the encroachment of a grown field oxide layer during MOS device fabrication by covering a masking anti-oxidant layer that defines the active element area of a semiconductor substrate with a layer of passivation material which extends over the edge of the anti-oxidant layer to contact the pad oxide over the semiconductor substrate surface.

Abstract: A technique for communicating digital data through a noisy medium using phase modulated carrier signals. A multiphase clock drives parallel channels to sample the received signal, avoiding the need for a phase locked loop. Data is recovered from the noisy carrier by a two stage statistical filtering technique and pattern analysis of the filtered signals.

Abstract: An output stage is disclosed wherein class AB bias is employed. The stage is quiescently biased by means of current mirrors so that the bias is controlled mainly by ratioed geometric elements. The output transistors are biased by means of unity gain common gate drivers that provide the desired level shifting. The output voltage can be swung from from close to the rail potential of the source of the n channel output transistor to close to the rail potential of the source of the p channel transistor. The circuit can drive relatively large load currents and can be fabricated using either CMOS or conventional bipolar integrated circuits.

Abstract: An FSK demodulator is disclosed suitable for use in a CMOS IC using switched capacitor circuits. The mark and space filters are each modified to produce sine and cosine outputs. These outputs are rectified separately and the result summed. The summed outputs are passed through low pass filters and applied to a comparator which determines which of the mark and space signals is dominant. The invention substantially reduces the size of the demodulator filter capacitors and improves the demodulation signal to noise ratio.

Abstract: A CMOS Schmitt trigger circuit responsive to TTL logic levels is disclosed. A supply regulator circuit renders the circuit independent of temperature, supply voltage and device parameters.

Abstract: A comparator circuit is disclosed wherein the input terminals are provided with a predetermined reference potential. Thus, in the case where only one input is driven the other input is biased at close to the reference. In the application of the circuit it is not necessary to provide an external package pin for reference potential.

Abstract: A hermetic ceramic semiconductor package is provided with impact absorbing bumpers by applying a composition of sealing glass loaded with malleable metal particles to the ceramic package. The bumpers are applied to the ceramic parts when they are being coated with sealing glass. When the hermetic package seal is formed the bumpers will form a metal loaded matrix that will absorb impacts and thereby avoid chipping of the ceramic package due to impacts during handling.

Abstract: An output stage suitable for monolithic semiconductor IC uses is disclosed. The stage employs a pair conventional NPN output transistors biased and driven with conventional bipolar IC elements. The pull up device, which sources output current for positive or rising inputs, is maintained on for negative signal swings so that it can be used to bias the pull down device which is cut off for positive signal swings.

Abstract: An AM stereo receiver decoder is shown. An AM detector produces the stereo L+R signal and a PM detector produces the L-R signal. The PM detector is created from a conventional FM detector that employs an input limiter driving a balanced multiplier. The limiter also drives a tuned circuit which provides quadrature drive to the multiplier. An integrator connected to the FM detector converts the response to a PM decoder. A large value inductor is simulated to appear across the integrator so as to create a low modulation frequency resonance at a subaudible frequency thereby providing a controlled pilot tone response. The inductor is simulated by the action of a first G.sub.m amplifier driving a capacitor which drives a second G.sub.m amplifier having an output coupled back to the input of the first G.sub.m amplifier. The capacitor is switched by means of a series connected switch that disconnects the capacitor when the AM exceeds a predetermined value.

Abstract: A current mirror using NPN transistors is described for use in PN junction isolated monolithic integrated circuits. A preferred embodiment operates at high accuracy over a wide range of output currents. It also operates at a relatively high signal frequency. An application in a charge pump, suitable for use in a digital phase locked loop, is detailed.

Abstract: A Darlington output stage is shown in which the saturation voltage is substantially reduced by the incorporation of a complementary transistor. An IC form of the circuit is shown in detail.

Abstract: A compensation arrangement is shown for the diffused column line resistance in an N channel metal gate read only memory. The circuit employs a dummy column which has a transistor at each possible location operated from the same decoder that operates the metal gate rows. A current sense circuit clamps the column pull-up end of the dummy column line and provides a correction signal that is fed to the pull-up devices in the memory columns. A second current sense circuit clamps the dummy column sense amplifier end of the column line and provides a correction signal that can be used to compensate the reference currents in column sense amplifiers using differential current sensing.

Abstract: A static random access memory array cell that is non-volatile because when power fails a floating gate is charged or not charged depending on the information content of the cell. When power is restored, all cells are written to a positive state except those with charged floating gates so that the information content of the array is recreated.

Abstract: A process is disclosed for making CMOS transistors in combination with self-aligned fully oxide isolated Schottky clamped bipolar transistors.

Abstract: A circuit that monitors the LED driver output pins on an integrated circuit for quiescent moments and then uses those output pins, only during these moments, to strobe keys on a keyboard for input signals.

Abstract: A switching circuit is employed to control the flow of energy from a power source to a tuned load. The control is achieved by means of a pulse width control voltage. The load current is sensed and fed to a phase locked loop which contains an oscillator producing an output that is slightly above load resonance. The phase locked loop forces the circuit to operate at a frequency where the modulating pulses are initiated at the load current zero crossing. The circuit is shown in use in a regulated d-c power supply and in a fluorescent lamp power supply application.

Abstract: An adhesive composition for attaching semiconductor die to a substrate of a semiconductor device package includes a crosslinkable resinous polyimide, and an aminosilane crosslinking agent. For applications where backside contact to the semiconductor die is desired, the composition also contains finely divided conductive metal, such as silver flakes. When used in a novel process in which the adhesive composition is placed on the semiconductor device substrate prior to gelling, outgassed, a semiconductor die is placed on the outgassed composition, and the composition cured, the resulting semiconductor device package meets military specifications with a substantial cost reduction.

Abstract: A gang bonding interconnect tape for use in an automatic bonding machine for gang bonding of semiconductive devices is fabricated by depositing a series of electrically insulative support structures, such as rings of epoxy resin, onto a metallic tape, as of copper, there being at least one of said electrically insulative support structures for individual ones of the interconnect lead patterns to be formed in said metallic tape. The side of the metallic tape, opposite to the support structure, is photoetched with a series of interconnect lead patterns with individual ones of said lead patterns being etched in registration with individual ones of said electrically insulative support structures. The individual electrically insulative support structure, preferably in the form of a ring, is located in each of the lead patterns intermediate the central region thereof and the outer region thereof for supporting the individual leads thereof in circumferentially spaced relation.