Abstract: An improved driver for differentially driving a differentially conducting cable (e.g., for Ethernet) minimizes the output offset signal coupled to the cable when the driver is idle. When driven to an idle state, the driver provides a shaped output which transitions to a quiescent output level in a manner which eliminates output signal common mode step change and consequently reduces signal distortion on the cable due to reflection of the step change.
Type:
Grant
Filed:
October 1, 1984
Date of Patent:
September 30, 1986
Assignee:
National Semiconductor Corporation
Inventors:
Gabriel M. Y. Li, Charles P. Carinalli, Ramanatha V. Balakrishnan
Abstract: A peak-to-peak signal detector circuit is disclosed. It can be directly coupled and rejects any d-c component associated with the signal without requiring a coupling capacitor. The input is applied to separate positive and negative peak detectors the outputs of which are subtractively combined in an op-amp. A circuit application as a drop out detector in an optical disc system is detailed.
Abstract: An IC voltage regulator having a low dropout voltage is disclosed. A pass transistor driver is described in which the regulator quiescent current is reduced to a very small value.
Abstract: A splicer-welder (13) for multiple reels (11,12) of continuous tapes of multiple connected integrated circuit lead-frames to be conveyed through a lead-frame preparation line (10) includes fixed electrodes (40) positioned adjacent an entry slot (45) and spring-loaded movable electrodes (59) normally spaced from the fixed electrodes. The end of the lead-frame tape is sensed and by use of an accumulator section of multiple pulleys (18,19,20) one of which is movable on a rail (21), the span of tape between pulleys acts as a reserve of tape for continuous downstream processing of the tape while the end of the tape is stopped. Sprocket holes on the tape ends are placed on retaining pins (41,42) alongside the electrodes and one or more frames of a beginning of a second lead-frame tape from a second reel are overlapped with one or more frames of the end of the first tape.
Abstract: A non-impact form of thermocompression gang bonding of metal lead fingers to integrated circuit chip pads is disclosed. The method produces a plurality of simultaneously bonded chips using conventional heating means and totally avoids mechanical and thermal shock. The result is highly reliable bonding that results in exceptionally high bond strength.
Abstract: A differential amplifier is combined with a latch in a stage suitable for use in high speed comparators. An IC topography for the latch is also shown.
Type:
Grant
Filed:
February 13, 1984
Date of Patent:
August 19, 1986
Assignee:
National Semiconductor Corporation
Inventors:
Thomas M. Frederiksen, Daniel D. Culmer
Abstract: A totem pole output stage is shown where current spikes are minimized. The circuit disclosed employs four transistors and three diodes to eliminate the spikes associated with the input low to high transition. A fourth diode minimizes the input high to low transition time.
Abstract: A CMOS comparator circuit is disclosed in which a low offset is achieved without trimming. The input stage is composed of a pair of bipolar transistors which have lateral non-dedicated collectors that operate in parallel with the substrate dedicated collectors. The input stage includes matched load devices and is followed by an amplifier having a differential to single ended converter.
Abstract: An integrated circuit includes a plurality of circuit elements interconnected to operate as a circuit and formed in a common semiconductor substrate. The substrate is mounted on a supporting package, resulting in a mechanical stress in the substrate which is symmetrical about at least one given axis. At least the circuit elements with operating characteristics which are altered by the mechanical stress and which have a critical matching or ratio relationship are arranged symmetrically about the stress axis of symmetry. In a preferred form, the integrated circuit is a linear circuit, such as an operational amplifier employing junction field effect transistors (JFETs) for its input stage and bipolar transistors for its amplifier stage. Providing device symmetry about an axis of mechanical stress symmetry enables shifts in input offset voltage for such operational amplifiers to be reduced up to a factor of about 10.
Abstract: A system for electroplating metals, such as tin and solder on semiconductor lead frame strips includes a magazine for carrying the lead frames and a separate plating rack for carrying the magazines. The plating rack, which has an insulated surface, includes means for directing a current to the lead frame strips when the magazine is inserted in the plating rack. An electric coupling means is also provided for assuring that the current from the plating rack is evenly distributed among the individual lead frame strips so that uniform plating results. The magazine is suitable for transporting and storing the lead frame strips during assembly of semiconductor components, and it is unnecessary to remove the lead frame strips from the magazine for mounting on the plating rack.
Abstract: A CMOS circuit is disclosed for developing a proportional to absolute temperature output current and a temperature invariant semiconductor bandgap voltage.
Abstract: A heat exchanger for cryogenic liquid evaporation is shown. A coil of tubing is coupled to the source of cryogenic liquid and heated by the flow of water. The other end of the coil is the gas exit at about atmospheric pressure. The gas back pressure in the coil is employed to self regulate the flow of cryogenic liquid into the heat exchanger.
Abstract: A metal resistor having a positive temperature coefficient of resistance is connected to a current source to develop a voltage drop that acts as an offset for a .DELTA.V.sub.BE differential amplifier. Since this offset voltage has a positive temperature coefficient it will compensate the resistor coefficient to develop a constant current. The constant current can be employed in a current sink sense-shutoff combination or it can be used to develop a plural output current source/sink combination.
Abstract: A voltage controlled oscillator circuit is disclosed. A CMOS circuit version is detailed. A relaxation oscillator has its input coupled by way of a voltage follower buffer to the input terminal where the control voltage is applied. The operating frequency is determined by the circuit resistor and capacitor values along with the control potential. A linear frequency versus voltage response is obtained and the circuit will operate at low supply voltages.
Abstract: A method for solder plating metal leads in plastic semiconductor packages comprises cleaning the leads followed by electroplating tin or a tin/lead alloy onto the leads. The cleaning is effected with a non-corrosive solution which is either a carboxylic acid, a hydroxycarboxylic acid, or a combination of both. The electroplating solution is a sulfonic acid or citric acid based system, including suitable tin salts and/or lead salts. A sequestering agent may be used to inhibit the corrosive effect of the electroplating bath.
Type:
Grant
Filed:
June 3, 1985
Date of Patent:
May 20, 1986
Assignee:
National Semiconductor Corporation
Inventors:
Vijay M. Sajja, Ranjan Mathew, Jagdish Belane
Abstract: A low noise oscillator is described suitable for use in an AM stereo radio receiver. The oscillator circuit includes means for controlling its amplitude at a constant low level. The oscillator is amenable to electronic tuning and IC construction.
Abstract: A high capacitance/low leakage capacitor for use in a dynamic RAM cell fabricated from a metal silicide or metal silicide/poly capacitor plate structure, with formation of an anodic metal/silicon/oxygen insulating film over that structure.
Abstract: A class B IC transistor output stage, using a pair of NPN transistors, is described. A quasi-complementary transistor is employed to establish the stage quiescent bias. An NPN bias transistor is coupled to the output sink transistor and is driven from the emitter of the input driver transistor. Therefore, the input signal is coupled to apply the signal directly to the base of the sink transistor as well as to the source transistor. This feedforward arrangement by-passes the PNP transistor when a signal is applied so that the asymmetrical performance of the PNP transistor does not adversely affect the signal performance.
Abstract: A class AB monolithic silicon IC output stage is shown wherein the main output transistors are NPN structures. The current sourcing transistor is provided with an additional scaled down reference emitter and the two emitters connected to the inputs of an op amp which has its output coupled to drive the current sink transistor. The base of the current source transistor is driven from a high gain driver transistor stage which may also contain a d-c level shifter that permits the inclusion of a complementary current sink transistor that can greatly reduce cross-over distortion while conducting only quiescent current.
Abstract: The plating apparatus (10) includes a pair of loop belts (20,21) rotating on two sets of pulleys, each set of pulleys including pulleys (11,12), to drive a strip (40) to be stripe plated past a translatingly movable electrolyte manifold (41) containing a series of electrolyte inlet and outlet slots (70,71) in its strip-facing surface. Electrolyte is sprayed from the inlet slots through apertures (24) in a back-up layer of at least one of the belts and through a slot (22) formed between belt segments. Vacuum or air pressure inlets (78,96) are provided at the ends of the manifold to prevent egress of electrolyte from the nip between the pairs of belts. One pulley of each set of pulleys is adjustable to tension the belt and an intermediate roller arrangement is included between each of the pulleys in each set to monitor the belt tension and provide sufficient frictional holding contact between the belts and the workpiece strip and desired sliding contact between the belts and the manifold surface.