Abstract: A method of plating bumps on metallization on the face of a wafer, including the steps of placing the wafer in a transportable fixture wherein cathode needles press against the face of the wafer to make electrical contact and to force the back side of the wafer against a sealing member to prevent the plating bath from contacting the back side. The fixture with the wafer therein is placed in a clean up or presoak bath and is then transported to a plating bath without an operator having to touch the wafer.

Abstract: A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.

Abstract: A process module which is compatible with a system using vacuum wafer transport in which wafers are generally transported and processed in a face down position under vacuum, and which also includes an additional wafer movement, wherein, after a wafer has been emplaced face down, in a position where it can be clamped against the susceptor, the susceptor is rotated from its approximately horizontal position up to a more nearly vertical position. In the more nearly vertical position, the wafer can be processed by a top process module, which may be, e.g., a sputter system, an implanter, or an inspection module. Another process module is included in the bottom part of the chamber, so that the wafer can be processed by the lower process module while in its substantially horizontal position and processed by the upper process module when it is in its more nearly vertical position. This is especially advantageous when the lower process module is a plasma cleanup module and the top module is a deposition module.

Abstract: Apparatus for the temporary storage of load locks to prevent accidental loss or theft during times when the load locks are not being used. The apparatus comprises a storage rack including a first swivel plate hinged upon a second swivel plate, which in turn is hinged upon a base plate to be mounted on an interior wall of a truck trailer. The apparatus further includes transverse support bars, first and second pairs of clamps, and a lock bar arranged to secure one pair of clamps in the closed position to prevent removal of the load locks.

Abstract: The sheet resistance of an integrated circuit wafer (W) may be measured during an integrated circuit fabrication process step. A chamber (26) has disposed therein a plurality of probes (40) each having a conductive tip (84) for abutting the work surface at a respective preselected location thereon. A current source (52, 114) is connected by at least two conductors (118, 112) between at least two of the tips (110, 116). A voltmeter (50) is connected between at least two of the tips (120, 126) by further conductors (122, 124). The voltmeter (50) is read out while the process step is being performed, and the voltage is converted to a sheet resistance according to the preselected electrical configuration of the circuit and a predetermined formula.

Abstract: An optical analyzer and a developer recirculation system is used to determine the amount of photoresist polymer dissolved in a quantity of developer solution and the sensor output signal is utilized by a control computer to control the admission of fresh developer solution to replace used developer and maintain a fixed level of dissolved photoresist polymer to keep the developer bath at a fixed level of chemical activity.

Abstract: A reflective beam of light is used to analyze the optical transmission properties of a developer fluid during puddle develop of photoresist polymer for detercting the process endpoint.

Abstract: The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group.

Abstract: The invention relates to a field-effect transistor (1;20) with insulated gate electrode (9;30) which comprises in a semiconductor body (5) a drain diffusion zone (2) connected to a drain electrode (6;32) and a source diffusion zone (3) which is disposed spaced from the drain diffusion zone (2) for forming a channel zone (4) and which is connected to a source electrode (7). The gate electrode (9;32) of said field-effect transistor is disposed on a gate insulating layer (8) over the channel zone (4). For protecting the transistor against high voltages produced by electrostatic charging the drain diffusion zone (2) of the transistor and/or the source diffusion zone (3) between the respective associated electrode (6,7;32) and the channel zone (4) is divided into a plurality of parallel strips (10,11). Integrated circuits are also protected against destruction by high voltages if the insulated gate field-effect transistors connected to their output terminals are constructed in the manner outlined above.

Abstract: An electron beam apparatus in which the electron beam is directed to a sample and secondary electrons from the sample return in the direction of the beam and are deflected sideways to a collector by a first electrostatic deflection means. To compensate for distortion of the spot produced by the beam as a result of the first electrostatic deflection means, a similar deflection means is placed above the first means to correct the distortion and is so biased as to reflect secondary electrons which might otherwise pass the first means. The deflection means are 4-pole electrostatic stigmators. A threshold grid is biased to allow to pass to the first means only those secondary electrons having release speeds from the sample above a certain value.

Abstract: Device for the testing and checking of the operation of blocks within an integrated circuit, characterized in that it is formed from a set of shift registers and logic circuits associated with each block of the circuit to be tested, the set of registers including at least one test register (35), one status register (36) and one mask register (37), the status register (36) being connected to the outputs (ST0 to ST15) of the block to be tested while the test and mask registers (35,37) and the logic circuits (38,39) are connected to a central processing unit (1) of the integrated circuit of which the blocks form part, the central processing unit (1) being also connected to the said blocks (7,10) by a common interrupt line (.SIGMA.INT).

Abstract: Charged particles from a line emitter are focussed as a line image on a means for selectively blocking part of the image to produce a flat beam of controllable length. The blocking means may be an apertured plate with means for rotating and/or translating the image relative to the aperture to produce the required beam length. After passage through the aperture the beam may be twisted and/or translated to its original or some other orientation and position. The beam may be of electrons or ions and may be used in the manufacture or testing of integrated circuits. An alternative form of blocking means is a row of controllable gate electrodes which can block selected parts of the line beam; this is of particular value in producing c.r.t. displays.

Abstract: An apparatus and a method for monitoring the functioning of an integrated circuit in operation using an electron beam directed to a particular node of the circuit which is of interest and measuring the energy of the secondary electrons emitted, in which the energy measurement is made using a filter grid, the bias on which is set by comparing a voltage representing the rate of receipt of secondary electrons past the filter grid with a reference voltage and adjusting the bias in response to the comparison so as to reduce the number of electrons received. A current is produced proportional to the difference between the two voltages and applied to charge a capacitor, the voltage on which is used to set the voltage on the filter grid.

Abstract: An acceleration sensor uses a capsule of mercury filling a rigid enclosure with pressure sensors responsive to inertial forces exerted by the mercury on the walls of the enclosure when it is caused to accelerate. The enclosure may have a flexible lining on its walls or contain a flexible bag for holding the mercury. Means are provided for producing a bias pressure in the mercury. The enclosure may be cubic or tetrahedral, for example, and the outputs of the pressure sensors additively combined to produce outputs representing accelerations in required orthogonal directions when these differ from the directions to which the sensors are responsive. A rotational acceleration sensor is also described.

Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.

Abstract: A heterojunction transistor has an acceptor doped superlattice base of sub-micron thickness, a composite emitter with a donor concentration adjacent the base, with a wider bandgap energy than the base, and with a low recombination velocity to minimize minority carrier diffusion and to set the divergence of emitter and base carrier velocities, and a collector configured like the emitter, permitting control and optimization of the cut-in voltage. The method for making the transistor includes forming the base, emitter, and collector by non-compensated, non-planar wafer processing techniques.

Abstract: A bipolar power transistor having a plurality of elongated emitter parts connected to a common emitter metallization is provided with a shaped resistive region between the emitter parts and the emitter metallization, in order to compensate for differences in the resistance presented by the metallization itself.

Abstract: The point processor includes a network of memory cells (33) addressable into rows and columns (direction X and Y). A control unit (42) effects reading and writing into the network according to parameters established in advance. This processor is integrated into a video display system for various image manipulations.

Abstract: A semiconductor contact system controls the boundary recombination velocity and optimizes the semiconductor transport phenomena and includes a microcrystalline layer of doped semiconductor microcrystals surrounded by a semiconductor oxide. The microcrystalline layer is acceptor and oxygen doped to provide unipolar hole transport and donor and oxygen doped to provided unipolar electron transport. The oxygen doping is implanted several atomic layers into the semiconductor to form a gradient between the semiconductor and microcrystalline layer to preserve the semiconductor monocrystalline lattice. The thickness of the microcrystalline film is adjusted to be thick enough to control the effective chemostatic potential terminating the semiconductor and thin enough to enhance the series microcrystalline film resistance.

Abstract: A test circuit for a VLSI integrated circuit includes interface test circuits (20) which are disposed between a logic circuit (16) an output terminal (14). The interface circuits (20) are each operable to provide a transparent interface between logic circuit (16) and output terminals (14) or force a high logic state on the output, a low logic state on the output or a floating state. A test code circuit (22) is operable to receive two logic signals from pins (24) and (26) external to the IC and determine the state of the test interface circuit (20) such that all test interface circuits (20) operate simultaneously in the same mode.