Abstract: A phase error circuit including phase difference logic and delay and register logic. The phase difference logic provides a pulse difference signal including at least one difference pulse indicative of a timing difference between selected edges of a pair of clock signals. The delay and register logic receives the pulse difference signal and provides a phase error value representing phase error between the clock signals. The delay and register logic may include a delay line with multiple delay cells and taps coupled in series in which each tap provides an output state of a delay cell. The register logic registers a state of each tap to provide delay bits in response to each trailing edge of the difference pulses. Each delay bit may remain set until reset so that the longest pulse difference signal is registered to provide the peak phase error.

Abstract: A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level.

Abstract: A method of making a coding mode decision for a current macroblock of a current video frame including determining an INTERSAD value, selecting at least one video characteristic associated with the current video frame, comparing the INTERSAD value with a corresponding range of each selected video characteristic, selecting interframe coding if the INTERSAD value is within the corresponding range of each selected video characteristic, performing intraframe prediction to provide an intraframe prediction macroblock and determining an INTRASAD value if the INTERSAD value is an outlier of any selected video characteristic, selecting intraframe coding if the INTERSAD value is greater than the INTRASAD value and otherwise selecting interframe coding. The video characteristics may be based on any combination of an average of interframe differential sums, a sum of absolute differences between each pixel value of the current macroblock and a mean pixel value of the current macroblock, and a quantization parameter.

Abstract: A controller for a switching regulator is disclosed including a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal, and references the filtered sense signal and the error signal to a common DC level. The comparator circuit develops a pulse control signal used to control switching of the pulse switch circuit based on comparing the error signal with the filtered sense signal.

Abstract: A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase.

Abstract: A method of de-interlacing interlaced video information including determining functional equations which estimate trajectories of corresponding pixel locations based on statistical information, updating each functional equation with sampled pixel values from the interlaced video information of corresponding pixel locations, and evaluating the functional equations at a time point of a progressive frame and providing corresponding progressive pixel values. A video de-interlace system including a trajectory estimator and a component estimator. The trajectory estimator provides functional equations estimating trajectories of tracked pixel locations based on statistical information. The component estimator receives the functional equations and the interlaced video information and provides progressive pixel values.

Abstract: A passive wireless receiver to receive an input signal and passively process the input signal to generate an output signal. An embodiment of the receiver includes an input circuit, a dynamic switching circuit, and a switch signal generator. The input circuit is configured to receive an input signal and produce a first output signal. The input circuit includes a passive network configured to condition the input signal. The dynamic switching circuit is configured to perform frequency translation on the first output signal. The switch signal generator is configured to drive the dynamic switching circuit to activate and deactivate the dynamic switching circuit at a sampling frequency that is controlled and stabilized by a frequency control circuit.

Abstract: A pulse control system for a multiphase regulator including an error amplifier, a multiphase generator, and an adaptive controller. The error amplifier provides an error signal indicative of output voltage error. The multiphase generator develops modulation pulses for phases based on the error signal. The adaptive controller is responsive to a load indication signal and redirects at least one modulation pulse from a first of phase to a second phase. The load indication signal may be received from a microprocessor indicating a low power mode. The adaptive controller provides a smooth and efficient transition to low load conditions by dropping operation of one or more phases and redirecting modulation pulses to the remaining one or more phases, and reduced phases improve power efficiency for the low load conditions.

Abstract: A current sense amplifier sensing current through a main switch of a converter. The amplifier includes first and second switch devices, an amplifier control circuit, a bias circuit, a current generator circuit, and a sense circuit. The main switch is coupled to an input, phase and control nodes. The first and second switch devices are smaller matching versions of the main switch and are both coupled to the main switch and form first and second nodes. The bias circuit is coupled between second and fourth nodes and the amplifier control circuit is coupled between first and third nodes. The current generator develops a first current through the amplifier control circuit and a second current through the bias circuit. The sense circuit has a current path coupled to the first node and is controlled by the third node to develop a sense voltage indicative of current through the main switch.

Abstract: A boost regulator for converting an input voltage to a higher output voltage including an inductor, an error circuit, a switching circuit, a ripple circuit, and a hysteretic comparator circuit. The inductor has a first end coupled to the input voltage and a second end. The error circuit determines an error of the output voltage and provides an error voltage indicative thereof. The switching circuit switches the second end of the inductor between the output voltage and ground as controlled by a pulse width modulation signal. The ripple circuit synthetically replicates ripple current through the inductor based on voltage applied across the inductor and provides a ripple voltage indicative thereof. The hysteretic comparator circuit develops the pulse width modulation signal based on comparing the ripple voltage within a hysteretic window voltage range based on the error voltage.

Abstract: A modulator circuit for a switching regulator including first and second ramp generators, a comparator circuit and a reset circuit. The switching regulator provides a compensation voltage indicative of output voltage error. The ramp generators generate leading- and trailing-edge ramp voltages which are compared to the compensation voltage for determining pulses on a pulse modulation signal. The reset circuit prevents the leading-edge ramp voltage from resetting if the leading-edge ramp voltage has not reached the compensation voltage while ramping. The reset circuit further clamps the leading-edge ramp voltage until the pulse modulation signal is asserted again. In a multiphase configuration, each leading-edge ramp voltage is suspended if any leading-edge ramp voltage is clamped. An offset voltage may be added to the compensation, leading-edge, or trailing-edge voltages when a mode select signal indicates a reduced load condition. The offset voltage may be adjusted based on various operating conditions.

Abstract: A method of adaptively adjusting a QP of a video encoder to control output bit rate including estimating the QP based on a complexity of a previous frame and encoding bit rate information of a current frame to provide an estimated QP, determining a threshold value based on a video quality factor, a target bit rate and a complexity of a previous interval of the current frame or the same interval of the previous frame, and if the estimated QP is greater than the threshold value, adaptively adjusting the estimated QP using the threshold value, the target bit rate and the complexity of the previous interval. The method may include adaptively limiting a change of the QP between frame intervals based on a difference between the QP and the threshold value. Complexity information may be based on an average of minimum SAD values.

Abstract: A method of fast predictive automatic gain control is disclosed including estimating channel gain applied to a received signal, predicting channel gain at a subsequent time by applying temporal correlation statistics to the estimated channel gain, determining a predicted receiver gain which reduces variance between the predicted channel gain and a predetermined target power level, and applying the predicted receiver gain to the received signal. The method may include applying linear minimum mean-squared error prediction to the estimated channel gain. The method may include predicting error variance at the subsequent time by applying the temporal correlation statistics to the estimated channel gain and combining the predicted channel gain and the predicted error variance.

Abstract: A docking light system for a watercraft including a docking light fixture, a docking lamp positioned within the docking light fixture, and an accessory lamp mounted to the docking light fixture. The accessory lamp emits light outwardly from the watercraft and is masked to control the horizontal and vertical beam spread sectors of emitted light from illuminating the watercraft causing glare to an occupant of the watercraft. In another aspect, a navigation light is provided on the docking light fixture, where the navigation light may be a masthead light, a stern light, a port side marker light, a starboard side marker light, etc.

Abstract: A current sensing circuit with AC and DC temperature compensation for sensing current through an output inductor which has an inherent DC resistor with a temperature varying resistance. A first RC circuit is coupled across the output inductor and has a time constant. The first amplifier provides a sense signal indicative of voltage of the first RC circuit. The second RC circuit is coupled to a first correction node and receives the sense signal. The second resistor has a temperature varying resistance so that the second RC circuit has a time constant commensurate with a time constant of the output inductor. The third RC circuit is coupled to a second correction node and has a time constant equal commensurate with the first RC circuit. The second amplifier provides a corrected sense signal based on the correction nodes.

Abstract: A universal serial bus power control circuit including at least one first switch which selectively couples a power source node to an external power node, a comparator which detects when the external power node is charged, a feedback node for enabling voltage regulation, a charge circuit and a controller. The charge circuit charges the external power node from the power source node and selectively couples the feedback node to at least one of the power source node and the external power node. The controller opens the first switch when the external power node is not charged, controls the charge circuit to charge the external power node while coupling the feedback node to the power source node, and closes the first switch and couples the feedback node to the external power node in a host mode when the external power node is charged.

Abstract: A buck-boost regulator for converting an input voltage to an output voltage which includes an inductor, an error circuit providing an error voltage, buck and boost switching circuits, buck and boost ripple circuits, and buck and boost hysteretic comparator circuits. The buck switching circuit switches a first end of the inductor, the buck ripple circuit replicates ripple current through the inductor based on the buck pulse signal and provides a buck ripple voltage, and the buck hysteretic comparator circuit develops the buck pulse signal based on a buck window voltage range using the error voltage. The boost switching circuit switches a second end of the inductor, the boost ripple circuit replicates ripple current through the inductor based on the boost pulse signal and provides a boost ripple voltage, and the boost hysteretic comparator circuit develops the boost pulse signal based on a boost window voltage range using the error voltage.

Abstract: An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin.

Abstract: A method of controlling access to a restricted area including receiving location information from at least one supplemental tracking source which tracks location of an authorized user, and controlling access by the authorized user to a restricted area based on the location information. The method may further include maintaining a muster based on the location information. A physical access control system for controlling access to a restricted area including a user location information system and an access system which controls access based on the location information. The user location information system may further maintain a muster based on the location information. The user location information system receives location information indicating location of an authorized user from at least one supplemental tracking source.

Abstract: A synthetic ripple regulator including a synthetic ripple voltage generator that generates a synthetic ripple voltage indicative of the ripple current through an output inductor. The regulator uses the synthetically generated ripple voltage to control toggling of a hysteretic comparator for developing the pulse width modulation (PWM) signal that controls switching of the regulator. In a non-limiting implementation, a transconductance amplifier monitors the phase node voltage of the inductor and supplies an inductor voltage-representative current to a ripple capacitor, which produces the synthetic ripple voltage. Using the replicated inductor current for ripple regulation results in low output ripple, input voltage feed forward, and simplified compensation.