Abstract: A modulator control circuit including a linear control circuit, a non-linear control circuit, and a combiner. The linear control circuit has an input receiving a compensation signal indicative of an output parameter and an output providing a first control signal. The non-linear control circuit has an input receiving the compensation signal and an output providing a second control signal. The non-linear control circuit senses transients of the compensation signal not otherwise detected by the linear control circuit and asserts the second control signal indicative thereof. The combiner combines the first and second control signals to provide a pulse width modulation signal for controlling the output parameter, such as output voltage or the like.

Abstract: A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, which provides one of multiple sparse memory write transactions on the request signals and which provides corresponding enable bits on the address signals. Each sparse memory write transaction corresponds with one of multiple granularities of data. For example, if the sparse memory write transaction is a quad-pumped cache line write for eight quadwords, the enable bits may be a selected one of byte, word, doubleword, quadword, doublequadword, etc., enable bits. A method of performing a sparse write transaction including providing an address and a request for a memory write transaction, indicating that the memory write transaction is a selected sparse write transaction, asserting enable signals for the selected sparse write transaction, and providing data for the sparse write transaction.

Abstract: A method of dynamically configuring a temperature profile in an integrated circuit (IC). The method includes sensing temperature of the IC, configuring a reduced operating temperature range for the IC, and modulating at least one control mechanism to maintain the temperature of the IC within the reduced operating temperature range. The configuring includes precluding configuration of the reduced operating temperature range at unauthorized privilege levels.

Abstract: A dual-edge modulation controller including first and second ramp circuits, first and second comparators, an error amplifier and pulse control logic. The first ramp circuit provides a leading-edge ramp synchronous with a clock. The error amplifier compares a feedback signal with a reference and provides a compensation signal. The first comparator compares the leading-edge ramp with the compensation signal and asserts a set signal. The second ramp circuit provides a trailing-edge ramp that begins ramping when the set signal is asserted. The second comparator compares the trailing-edge ramp with the compensation signal and asserts a reset signal. The pulse control logic asserts a PWM signal when the set signal is asserted and de-asserts the PWM signal when the reset signal is asserted. The controller may control multiple phases with current balancing. The slew rate of the ramps may be adjusted based on the number of PWM signal asserted.

Abstract: An adaptive pulse positioning system for a voltage converter providing an output voltage, the system including a PWM generation circuit, a sensor, and a pulse positioning circuit. The PWM generation circuit generates a PWM signal with PWM pulses for controlling the output voltage of the voltage controller. The sensor senses an output load condition of the voltage converter and provides a load signal indicative thereof. The pulse positioning circuit adaptively positions the PWM pulses based on the load signal. A method of adaptively positioning PWM pulses that are used to control an output voltage of a voltage regulator including generating a series of PWM pulses based on a clock signal, sensing an output load condition, and adaptively shifting the series of PWM pulses based on the output load condition.

Abstract: A control circuit for a PWM switching power regulator including an error amplifier and an amplifier filter circuit. The error amplifier has a first input receiving a reference signal, a second input receiving an output sense signal, and an output providing a compensation signal used to control PWM switching. The amplifier filter circuit has an input receiving a ratio-metric tracking signal and an output providing the reference signal to the input of the error amplifier. The control circuit may include a resistive voltage divider for providing the tracking signal. The amplifier filter circuit may be implemented as a transconductance amplifier having an input receiving the tracking signal and an output coupled to a capacitor. The transconductance amplifier may have a relatively small current drive capacity and its output may have a relatively slow and weak response to changes of the tracking signal.

Abstract: A multiple channel programmable gamma correction voltage generator including a resistor ladder, buffers, select logic, and a programmable non-volatile memory device. The memory provides select values indicative of one or more stored gamma correction values. The resistor ladder includes adjustable tap resistors distributed along the resistor ladder. The adjustable tap resistors provide multiple tap voltages distributed according to the gamma correction value. The buffers receive the tap voltages and provide gamma correction voltages. The select logic selects tap points of the adjustable tap resistors to select the tap voltages based on the select values stored in the memory. Additional resistors and switch logic may be included to enable re-positioning of the adjustable tap resistor within the resistor ladder. Latches and address control may be provided on the memory to enable programming and selection of multiple gamma correction values.

Abstract: A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit generates a core clock signal enabling full speed operation of core circuitry of the IC during test mode. The pad clock circuit generates a preliminary clock signal suitable for normal operation, and the test clock circuit generates a test clock signal suitable for operating the I/O interface logic during the test mode. The select circuit selects, based on the test signal, between the test clock signal and the preliminary clock signal as the pad clock signal. The tester provides the bus clock signal and indicates the test mode to the DUT via the I/O interface logic.

Abstract: A microprocessor including processor logic and sparse write logic. The processor logic asserts address and request signals to provide an address and a request for a cache line memory write transaction. The sparse write logic causes the processor logic to modify a second part of the write request to specify the sparse write command value and to provide the corresponding enable bits. The sparse write-combined memory write transaction may be a quad-pumped cache line write transaction for writing eight quadwords in which each enable bit identifies a corresponding doubleword. A method of performing a sparse write-combined write transaction including providing an address and a request for a memory write transaction, indicating that the memory write transaction is a sparse write-combined write transaction, asserting enable signals for the sparse write-combined write transaction, and providing data for the sparse write-combined write transaction.

Abstract: An integrated device for sampling data packets asserted sequentially on a system bus, including a clock input for receiving a bus clock signal, a data bus interface for receiving the data packets and for detecting at least one data strobe indicating data validity, and dynamic source synchronized sampling adjust logic. The dynamic source synchronized sampling adjust logic includes sampling logic which selects and latches each data packet in response to the data strobe and which provides latched data packets, and select logic which selects from among the latched data packets based on a read pointer. A method of sampling data packets asserted sequentially on a data bus for one or more bus clock cycles including detecting operative edges of a data strobe, selecting a data packet for each detected operative edge, and latching each selected data packet.

Abstract: A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is transferred for each of four beats during each of four consecutive cycles of the bus clock. The data signal group may include multiple data strobes, such as first and second data strobes for latching first and third doublewords and third and fourth data strobes for latching second and fourth doublewords during each cycle of the bus clock. Each doubleword may be provided on first and second data portions of the data signal group. The first and second data strobes may latch data on the first data portion and the third and fourth data strobes may latch data on the second data portion.

Abstract: An interactive broadband server system including multiple processors, a backbone switch, multiple storage devices and multiple user processes. The backbone switch enables high speed communication between the processors. The storage devices are distributed across the processors to store titles, where each title is divided into data chunks that are distributed across the storage devices. The user processes are configured for execution on the processors for interfacing multiple subscriber locations. Each user process is operative to retrieve a requested title from two or more of the processors via the backbone switch and to assemble a requested title for delivery to a requesting subscriber location. The storage devices may be organized into RAID groups. Distributed media readers and a library storage system may be included. Multiple isochronous titles may be simultaneously delivered to downstream subscribers.

Abstract: A power management IC including a dual purpose pin, a fault detection system, and a fault signature system. The dual purpose pin performs a power management function during normal operation (e.g., a soft start pin coupled to an external capacitor, a set pin coupled to an external resistor, a frequency set pin coupled to a resistor-capacitor combination, etc.). The fault detection system senses any of multiple fault conditions and provides a corresponding fault indicator signal, each indicating a corresponding fault condition. The fault signature system generates a selected fault signature signal on the dual purpose pin, where each fault signature signal has a characteristic indicative of a corresponding fault condition. Thus, an existing pin on the IC is re-used to indicate the fault condition. The fault signature signal may be a unique voltage level, a unique charging rate, a unique frequency signal, or any a combination thereof.

Abstract: An overtone crystal oscillator automatic calibration system including an overtone crystal oscillator with multiple programmable resistors and multiple amplifiers with supply voltage inputs and a calibration system. The calibration system adjusts the programmable resistors and the supply voltage inputs and detects oscillation of the overtone crystal oscillator. The calibration system adjusts the programmable resistors and the supply voltage input for each of multiple sequential steps to adjust the frequency bandwidth, such as from a higher bandwidth and lower gain to a lower bandwidth at higher gain. For example, each resistance level is tested for each of multiple supply voltage levels. The range of resistances and voltages is designed to ensure oscillation at a selected overtone frequency while avoiding oscillation at a fundamental frequency of the oscillator crystal. Oscillation may be detected by a counter which counts to a predetermined count value indicating successful oscillation.

Abstract: An overtone crystal oscillator including a crystal, multiple amplifiers and an RC network. The crystal has a fundamental resonance frequency and at least one overtone resonance frequency. The amplifiers are coupled in series between terminals of the crystal and the RC network is coupled to the amplifiers. The amplifiers and the RC network are collectively configured to suppress oscillation of the crystal at the fundamental resonance frequency and to enable oscillation at an overtone resonance frequency of the crystal. The amplifiers and the RC network may be configured to cause a phase shift between the fundamental resonance frequency and the overtone resonance frequency. The overtone resonance frequency may be any odd harmonic of the fundamental frequency, such as a third overtone of the crystal. The overtone crystal oscillator may be integrated with CMOS processes and does not require an inductor to suppress the fundamental mode of oscillation.

Abstract: A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

Abstract: A digitally configurable multiplexer/de-multiplexer including several multiplexers, a switch matrix, and configuration logic. Each multiplexer receives multiple address signals, selects from among multiple first data signals and couples a selected first data signal to a corresponding one of several multiplexed signals. The switch matrix has a first interface coupled to the multiplexed signals and a second interface coupled to multiple second data signals. The configuration logic receives selection signals and controls the switch matrix to couple selected ones of the multiplexed signals to the second interface.

Abstract: An IC incorporating a multiphase voltage converter with synchronized phase shift including a phase shift pin, a frequency select pin, a master clock pin, and a voltage regulator. The phase shift pin is coupled to a first voltage for a master mode or a first resistor for a slave mode. The frequency select pin is coupled to one of a second voltage and a second resistor. The master clock pin provides a master clock signal or receives an external clock signal. The IC provides the master clock signal at a frequency determined by the second resistor or otherwise at a default frequency. The voltage regulator operates in the slave mode at a phase shift relative to the external clock signal based on the first resistor and the second resistor or based on the first resistor and a default resistance if the second voltage is coupled.

Abstract: An optical conversion device for a shared FTTH distribution network including first and second optical fibers and an optical processing circuit. The optical processing circuit has an input for receiving a first optical analog signal carried by the first optical fiber and an output for providing a first optical digital signal for transmission via the second optical fiber. The optical processing circuit is configured to digitize the first optical analog signal and incorporate into the first optical digital signal. The optical analog signal may be an optical signal which is modulated by an RF signal, which is the same or similar to that of existing HFC networks. High loss electrical signals are converted to low-loss optical signals propagated within the optical plant. The combined optical analog and digital protocol supports analogous communications of existing HFC networks and the optical plant minimizes cost of fiber optic upgrade.

Abstract: A wide linear range peak detector including first and second peak detectors and a compensation circuit. The first peak detector receives an input signal and has an output providing a first peak signal approximation which approximates a peak level of the input signal. The first peak signal approximation includes a non-linear portion which is a function of the peak level of the input signal. The second peak detector also receives the input signal and has an output providing a second peak signal approximation. The compensation circuit uses the second peak signal approximation to provide a compensation signal which compensates the non-linear portion of the first peak signal approximation. In particular, the second peak signal is used to generate the compensation signal to approximate and cancel the non-linear portion.