Abstract: A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.

Abstract: A clockless return to state domino logic gate is disclosed responsive to multiple input nodes including at least one return to state node. A domino circuit presets a preset node to a second state. The domino circuit switches to a latch state and switches an output node when the preset node is pulled to a first state, and resets back to the preset state and switches the output node back to its default state when a reset node is pulled to the second state. An evaluation circuit pulls the preset node to the second state when the input nodes are in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in its latch state. A reset circuit pulls the reset node to the first state after an evaluation event when the input nodes are no longer in the evaluation state.

Abstract: A memory system for an I/O controller which includes a memory with multiple memory blocks, a supply voltage control circuit providing power to each memory block, and control logic. Each memory block retains stored information with reduced power consumption when receiving a reduced voltage level. The control logic allocates buffers in the memory and controls the supply voltage control circuit to provide the full voltage level to at least one memory block of at least one allocated buffer and to provide the reduced voltage level to remaining memory blocks. Each memory block includes one or more buffers. In various embodiments the control logic fully powers each memory block of a buffer or less than all of the memory blocks. A linked buffer structure may be used to reduce the memory blocks of an allocated buffer receiving full power, such as only one memory block in the buffer.

Abstract: A method of de-interlacing input video information including averaging odd lines and averaging even lines of the input video information to determine first and second in-field information, determining differences between even and odd lines of the input video information to provide residue information, measuring a motion metric of the residue information, filtering the residue information based on the motion metric to provide filtered residue information, and combining the first and second in-field information with the filtered residue information to provide progressive information. The combining may be an average of the in-field information added to a weighted portion of the filtered residue information as determined by the motion metric. The motion metric may be determined by an infinite impulse response filter. Finite impulse response filters may be used to filter the residue information.

Abstract: A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.

Abstract: A method of time resolved radiation assisted device alteration testing of a semiconductor circuit which includes performing spatially resolved radiation assisted circuit testing on the semiconductor circuit while applying a test pattern to determine a pass-fail modulation location, asynchronously scanning the semiconductor circuit with radiation while repeatedly applying the test pattern and providing pass-fail results, combining corresponding pass-fail results provided during the asynchronously scanning to determine a shifted pass-fail modulation indication, determining time shift information between the pass-fail modulation location and the shifted pass-fail modulation indication, and identifying at least one of the test vectors based on the time shift information. The radiation may be a continuous wave laser beam.

Abstract: A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.

Abstract: A clockless return to state domino logic gate is disclosed responsive to multiple return to state input nodes. A domino circuit has a preset state in which it presets a preset node to a second state. The domino circuit switches to a latch state and switches an output node when the preset node is pulled to a first state. The domino circuit resets back to the preset state and switches the output node back to its default state when a reset node is pulled to the second state. An evaluation circuit pulls the preset node to the second state when the input nodes are in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in its latch state. A reset circuit pulls the reset node to the first state after an evaluation event when the input nodes are no longer in the evaluation state.

Abstract: A clockless return to state domino logic gate including a domino circuit and an input circuit. The domino circuit asserts s preset node and an enable node to a first logic state and asserts an output node and a reset node to a second logic state in a preset state, and switches to a latch state when the preset node is pulled to the second state. In the latch state, the domino circuit pulls the output node to the first logic state and pulls the enable node to the second logic state. The domino circuit resets back to the preset state when the first reset node is pulled to the first logic state. The input circuit controls the domino circuit based on collective state of input signals, and is configured to perform a selected logic function using at least one return to state signal without use of a clock signal.

Abstract: A modulator for providing control pulses on a pulse control signal for controlling operation of a DC-DC converter is disclosed which includes a comparator, pulse control logic, a memory circuit and a switch circuit. The comparator compares a timing waveform with a compensation signal and provides a comparison signal with preliminary pulses. The pulse logic circuit receives the comparison signal and provides normal pulses on a normal pulse signal. The pulse logic circuit selects only those preliminary pulses which are provided during a permissible time window of each period of the periodic timing waveform. The memory circuit provides a pulse indication whenever a normal pulse does not occur on the pulse signal during any switching period. The switch circuit selects between the normal pulse signal and the comparison signal based on the pulse indication for providing the control pulses.

Abstract: A video encoder including a processing block and an external memory storing a current frame and a reference frame. The processing block includes a memory interface, a local memory and a processor. The processor encodes the current frame in raster scan macroblock order for FMO using information from the reference frame, converts encoded information into compressed information, and organizes the compressed information according to a predetermined FMO. The processor organizes the compressed information according to any suitable FMO organization such as scattered, interleaved, etc. The processor stores the compressed information into multiple slice groups into the local memory or into the external memory, where the slice groups are organized according to the FMO. The processor loads a search window macroblock into the local memory if not already stored in the local memory. The processor may generate unfiltered reconstructed information and store the unfiltered reconstructed information into the local memory.

Abstract: A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.

Abstract: An adjustable buffer including a series of P-channel devices having current paths coupled between a first voltage supply and at least one output node, and a series of N-channel devices having current paths coupled between the output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the output node. The selectable connections may be defined in an integrated circuit mask or may be electronic switches. The P- and N-channel devices may be in a balanced configuration or an imbalanced configuration. The P- and N-channel devices may form an inverting buffer or a non-inverting buffer.

Abstract: An error detection and correction circuit for a video decoder that reconstructs a lost macroblock including a clustering circuit, a classification circuit and an error concealment circuit. The clustering circuit clusters macroblocks adjacent to the lost macroblock into one or more defined clusters. The classification circuit assigns the lost macroblock or each sub-block of the lost macroblock to a defined cluster. The error concealment circuit reconstructs attributes of the lost macroblock or its sub-block based on selected attributes of a defined cluster to which the lost block is assigned. Clustering is based on entire adjacent macroblocks or sub-blocks thereof. The clustering circuit may perform clustering using any one or more of the attributes of the macroblocks including coding parameters, texture statistics, color components, frequency analysis, and image processing operators. The lost macroblock may be assigned as a whole or subdivided into lost sub-blocks that are individually assigned to clusters.

Abstract: A method of processing block-based image information including up sample filtering pixels located along boundaries of image blocks using a first filter strength and up sample filtering at least a portion of the pixels that are not located along boundaries of the image blocks using a second filter strength. The method may alternatively include up sample filtering pixels located along boundaries of image blocks and image sub-blocks using the first filter strength. An up sample filter system which includes a first up sample filter which filters pixels located along boundaries of the image blocks using a first filter strength and a second up sample filter which filters pixels that are not located along boundaries of the image blocks using a second filter strength.

Abstract: A decoder includes a sample rate conversion module, a decoding module, and an error sensing module. The sample rate conversion module is operably coupled to convert, based on an error feedback signal, rate of an encoded signal from a first rate to a second rate to produce a rate adjusted encoded signal. The decoding module is operably coupled to decode the rate adjusted encoded signal to produce a decoded signal. The error sensing module is operably coupled to produce the error feedback signal based on the decoded signal.

Abstract: A processing module including an interpolator, a demodulator, and a tracking module. The interpolator applies a feedback signal to a first digitized signal having a first data rate to produce a second digitized signal having a second data rate. The demodulator processes the second digitized signal to produce a digital composite signal having a timing component. The tracking module mixes the digital composite signal with a reference signal and produces the feedback signal. The tracking module may include a mixer, a filter, a comparator, a loop filter and a quantizer. The mixer and filter mixes an input signal with a reference signal to provide a filtered timing error signal. The comparator compares the timing error signal with a reference signal and produces an offset signal. The loop filter processes the offset signal to produce a filtered offset. The quantizer processes the filtered offset to produce the feedback signal.

Abstract: A headphone driver includes a driver module for generating a plurality of headphone driver signals including a filtered stereo sum signal.

Abstract: A method of locating a defect of a failed semiconductor device which includes applying a test pattern to the failed semiconductor device and providing failed semiconductor device test responses as a pass signature, applying radiation to each of multiple locations of circuitry of a correlation semiconductor device with sufficient energy to induce a fault in the circuitry, applying the test pattern to the correlation semiconductor device while the radiation is applied to the location and comparing correlation semiconductor device test responses with the pass signature for each location, and determining a defect location of the failed semiconductor device in which correlation semiconductor device test responses at least nearly match the pass signature. The radiation may be a laser beam. The method may include determining an exact match or a near match based on a high correlation result. Asynchronous scanning may be used to provide timing information.

Abstract: An adaptive pulse positioning system for a voltage converter including an adjustable ramp generator, a pulse generator circuit, and a sense and adjust circuit. The adjustable ramp generator has an adjust input and provides a periodic ramp voltage having an adjustable magnitude based on an adjust signal provided to the adjust input. The pulse generator circuit receives the ramp voltage and generates a pulse signal with control pulses for controlling the output voltage of the voltage controller based on the ramp voltage. The sense and adjust circuit senses an output load transient and provides the adjust signal to the adjust input of the ramp generator to adaptively shift the pulse signal in time in response to the output load transient without adding pulses to the pulse signal.