Abstract: An audio amplifier includes an output stage for generating an output stage voltage in response to an input signal and an output stage quiescent current. A controlled current source controls the output stage quiescent current in response to a quiescent current signal during a start-up cycle.

Abstract: A switch circuit including a first switch, a reference device, a current generating device and a comparator. The first switch has a first resistance and develops a first voltage when a first current is provided through it. The reference device has a second resistance which is a known multiple of the first resistance. The current generating device provides a reference current through the reference device which develops a second voltage having a level indicative of a maximum current level of the first current. The comparator compares the first and second voltages and provides a maximum current indication. An amplifier may be used to force one side of the first switch and the reference device to the same voltage, where the reference device is coupled between an input and an output of the amplifier. The switch circuit may include a calibration mode.

Abstract: A thrust bucket for use on a boat propeller including a plenum and a positioning system. The plenum includes a plenum wall with at least one water flow valve located on the plenum wall. The positioning system moves the plenum between inoperative and operative positions. The thrust bucket may include an annulus positioned in close proximity to a swept radius of the propeller when the plenum is in the operative position. The at least one operable water flow valve may be controlled to control a direction of water departing the plenum, or to control a quantity of water flow out of the plenum. The thrust bucket may further include a propeller guard mounted to the plenum and positioned at an inlet side of the propeller.

Abstract: An audio output driver includes an audio amplifier for generating an amplified signal. A virtual ground generator generates a virtual ground signal in response to a virtual ground reference. A combiner produces an output signal, based on the amplified signal and the virtual ground signal, that is coupled to an audio output device. A voltage equalizer equalizes the virtual ground reference and the output signal when the supply voltage compares unfavorably to a supply voltage threshold.

Abstract: A voltage regulation module which includes an adjustable voltage which reduces the positive supply voltage and increases the negative supply voltage during a lower power mode. The voltage regulation module includes a voltage generator which provides an N-type substrate bias voltage at the normal operating voltage level of the positive supply voltage and which provides a P-type substrate bias voltage at the normal operating voltage level of the negative supply voltage during the lower power mode. Thus, the supply voltage levels are adjusted rather than the substrate bias voltages during the lower power mode. The voltage generator may be implemented as a voltage regulator, or may be implemented as a bias generator or charge pump or the like.

Abstract: A multiphase regulator which includes an output node developing an output voltage, a feedback circuit determining error of the output voltage and providing a compensation signal indicative thereof, at least three phase circuits coupled in parallel to the output node, and an adaptive controller. Each phase circuit includes a modulation circuit and a switch circuit. Each modulation circuit receives the compensation signal and generates pulses on a corresponding one of the pulse modulation signals. Each switch circuit is coupled to the output node and is controlled by a corresponding pulse modulation signal. The adaptive controller is responsive to a load indication signal, such as indicating a low load condition, and drops operation of at least one of the phase circuits and adds at least one pulse to a pulse modulation signal of each remaining phase circuit.

Abstract: A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference between a reference oscillation and a feedback oscillation. The digital loop filter is coupled to process the difference signal to produce a control signal. The digitally controlled oscillation module is coupled to generate an output oscillation based on the control signal. The variable feedback divider is coupled to produce the feedback oscillation from the output oscillation based on a divider value and a controlled variable delay.

Abstract: A stereo decoder includes a first digital filter for producing a first filtered composite audio signal and a second digital filter for producing a second filtered composite audio signal. A sum/difference network produces a left channel signal and a right channel signal. A processor executes operational instructions that calculate a first corner frequency of a first digital filter based on a signal quality of the FM signal, calculate a first set of filter coefficients for the first digital filter based on the first corner frequency and an approximation of a filter transform, calculate a second corner frequency of a second digital filter based on the signal quality, and calculate a second set of filter coefficients for the second digital filter, based on the second corner frequency and the approximation of the filter transform.

Abstract: A synchronized data transfer system including storage processor nodes, a backbone communication switch, multiple titles subdivided into subchunks and distributed across the nodes, a user process executed on a first node, a transfer process executed on a second node, and a management process executed on a management node. The user process sends a timestamped read request to request a corresponding subchunk. The transfer process sends a message to the management process for each received read request, where each message identifies source and destination nodes. The management process broadcasts transmit commands to initiate sequential transmit periods, receives the messages, and selects from among the received messages to ensure that each node sends and/or receives no more than one subchunk at a time. The management process sends a transmit request for each selected message, and the transfer process sends a subchunk identified by a transmit request in response to the transmit command.

Abstract: A rate control system for a video encoder including rate control logic which determines a first QP corresponding to a selected encoding layer of multiple encoding layers, and scaling logic configured to scale the first QP to a second QP corresponding to any other encoding layer based on at least one encoding layer parameter. A template of stored QP values may be used to reduce computational complexity, such as a QP value for each frame interval or a QP value for each of multiple rate control interval complexity values. The QP values in the template may be predetermined or programmed and updated during periodic training sessions. Several encoding layer parameters are contemplated, such as any combination of bit rate, frame rate and frame resolution. The scaling logic may be configured to scale from any one encoding layer to another and vice-versa for bi-directional scaling.

Abstract: A network abstraction and isolation layer (NAIL) for masquerading the machine identity of a computer in a network to enable the computer to communicate in the network with a different machine identity including an isolated network interface for communicating with the computer, an abstraction network interface for communicating with a network device coupled to the network, and control logic. The control logic is coupled to the isolated and abstraction network interfaces and performs machine identity translation to masquerade machine identity of the computer relative to the network. Machine identity masquerading includes selectively translating any one or more of an IP address, a MAC address, a machine name, a system identifier, and a DNS Name in the header or payload of communication packets.

Abstract: A hysteretic mode controller for controlling a capacitor voltage divider which has a flying capacitor. In one embodiment, the hysteretic mode controller includes an amplifier, a gain circuit and a hysteretic comparator circuit. The amplifier has an input for coupling to the flying capacitor and an output providing a fly voltage. The gain circuit has an input for receiving the input voltage and an output coupled to a reference node providing a reference voltage. The hysteretic comparator circuit has a first input coupled to the output of the amplifier, a second input receiving the reference voltage, and an output for providing a PWM signal to control the capacitor voltage divider. The fly voltage is compared to voltage limits of a hysteretic voltage window for switching the PWM signal. The switching frequency is increased with higher load current to maintain high efficiency.

Abstract: A battery charging and power delivery system for a portable electronic device includes a first connection that connects the system to an AC/DC power adaptor. A second connection connects the system to the power bus of the portable electronic device. A third connection connects the system to a battery. A capacitor voltage divider circuit provides power to the system power bus through the second connection and provides power through the third connection. A controller provides control signals to the capacitor voltage divider and to the AC to DC power adaptor.

Abstract: A localized content adaptive filter system including a tile buffer having an output providing first image information, a frequency analyzer providing a frequency information signal based on frequency content of the first image information, and an adaptive filter which is adjusted based on the frequency information signal. The frequency analyzer may include a wavelet transform filter and a frequency content analyzer. The adaptive filter may include filter select logic which receives the frequency information signal and second image information associated with the first image information, and which provides filtered image information. The filter select logic determines a filter based on the frequency information signal and the determined filter filters the second image information to provide the filtered image information.

Abstract: A steady state frequency control circuit for a variable frequency regulator including an open loop frequency control circuit, a frequency detector and a comparator circuit. The variable frequency regulator provides a clock signal indicating actual operating frequency and has a frequency control parameter for adjusting steady state operating frequency. The frequency detector receives the clock signal and provides a frequency sense signal which is compared with a steady state frequency reference signal to provide a frequency adjust signal. The frequency control parameter is adjusted by the frequency adjust signal to control steady state frequency.

Abstract: An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set to a first reserved ROM address. After jumping the program counter to the first reserved ROM address, the program counter is jumped to RAM based on the RAM index to execute a patch code, which includes at least one instruction to set the program counter to a second reserved ROM address. When the program counter equals the second reserved ROM address, the ROM return address is retrieved. Then the instruction set is executed from ROM based on the ROM return address.

Abstract: An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.

Abstract: A switch circuit, which selectively couples first and second switch nodes together and which enables the first and second switch nodes to operate in an extended voltage range, includes a secondary voltage rail, a switch device, a body driver, a rail control switch, and a switch control circuit. The rail control switch clamps the secondary voltage rail to a primary voltage rail during normal voltage range operation, but otherwise releases the secondary voltage rail to float. The body driver clamps the body of the switch to the secondary voltage rail when turned on, and when turned off, forward biases to allow voltage of said secondary voltage rail to follow voltage of the switch nodes into the extended voltage range through the switch. The switch control circuit includes a latch circuit which ensures that the switch remains either turned on or turned off during extended voltage operation.

Abstract: A motion stabilization system including a filter bank and motion stabilization logic. The filter bank receives a video signal and provides at least one high frequency sub-band signal which includes edge information of the video signal. The motion stabilization logic receives the high frequency sub-band signal, a reference image, and the video signal and provides a stabilized image. The reference image is generated from image stabilization information developed during motion processing. The motion stabilization system may include an edge detector which receives and binarizes the high frequency sub-band signal. Binarization significantly reduces the amount of information to be processes by the motion stabilization logic. The motion stabilization system may further include a tile buffer which stores a portion of the video signal and which provides a video signal portion to the filter bank. The filter bank may be implemented as a discrete wavelet transformation filter.