Abstract: The present invention provides a method to adjustably sample a first digitized signal having a first data rate to produce a second digitized signal having a second data rate. This involves processing the second digitized signal to produce an output signal having a timing component contained therein. An error sensing module determines a timing error between the timing component and a digitized reference period. Then this timing error is used to produce a feedback signal that is applied to the sample timing of the first digitized signal. This allows the second digitized signal to be processed using a time domain associated with the second data rate.

Abstract: A fast motion estimation system that determines a reference macroblock or sub-block combination within a reference frame for a current macroblock in a current frame includes a memory, a reference macroblock search circuit, a sub-block combination search circuit, and a comparator circuit. The reference macroblock search circuit determines a motion vector, multiple difference values, and a cost value for each macroblock within the reference frame according to a fast motion estimation search pattern, and stores the motion vector and the difference values in the memory. The sub-block combination search circuit searches the motion vector and the difference values in the memory for determining a corresponding one of multiple lowest cost sub-block combinations for each of multiple sub-block motion modes. The comparator circuit determines a lowest cost macroblock and selects from among the lowest cost macroblock and the lowest cost sub-block combinations to determine the reference macroblock.

Abstract: A navigation light system for a watercraft including multiple lights of a common color and that are spatially separated on the watercraft to collectively operate as a navigation running light that has a specified horizontal beam sector of less than 360 degrees. Each light is separately masked to emit light outwardly from the watercraft within a partial arc horizontal beam sector which is less than the specified horizontal beam sector. The navigation light system may include first and second running lights of first and second colors, respectively, where each running light includes multiple commonly-colored lights that are separately masked within a corresponding one of mutually exclusive partial arc horizontal beam sectors within the specified horizontal beam sector.

Abstract: A load compensation circuit for a switching regulator including a comparator circuit and an adjustable voltage source. The switching regulator includes a switch circuit for converting an input voltage to a regulated output voltage and for driving a load current, and a controlled switch driver circuit having a supply voltage input and an output driving the switch circuit. The comparator circuit senses the load current and adjusts a voltage control signal to adjust switching efficiency based on the load current. The voltage source has an input receiving the voltage control signal and an output for providing a switch supply voltage to the supply voltage input of the switch driver circuit, where the voltage source adjusts the switch supply voltage based on the voltage control signal. A method of compensating a switching regulator based on load including sensing load current and adjusting the switch supply voltage to adjust switching efficiency.

Abstract: An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided.

Abstract: A method of continuous testing of repetitive functional blocks provided on an integrated circuit (IC) which includes selecting one of the repetitive functional blocks at a time for testing, substituting a test repetitive functional block for a selected repetitive functional block, and testing the selected repetitive functional block during normal functional mode of the IC. An IC which includes repetitive functional blocks for performing corresponding functional block operations during normal functional mode of the IC, and a test system which performs continuous testing of each repetitive functional block while the functional block operations are performed during normal functional mode of the IC. One block may be tested during normal operation for each IC reset event without transferring or copying state information. Multiple blocks may be tested one at a time during normal operation by transferring state information between a selected block and a test block.

Abstract: An audio output circuit includes a DAC module, a line out circuit, and a headphone amplifier circuit. The digital to analog conversion (DAC) module is coupled to convert an audio component of digitized multimedia data into an analog audio signal. The line out circuit is coupled to amplify the analog audio signal based on a line out volume setting. The headphone amplifier is coupled to amplify the analog audio signal based on a volume setting to produce an amplified analog audio signal.

Abstract: A virtual file system including multiple storage processor nodes including a management node, a backbone switch, a disk drive array, and a virtual file manager executing on the management node. The backbone switch enables communication between the storage processor nodes. The disk drive array is coupled to and distributed across the storage processor nodes and stores multiple titles. Each title is divided into data subchunks which are distributed across the disk drive array in which each subchunk is stored on a disk drive of the disk drive array. The virtual file manager manages storage and access of each subchunk, and manages multiple directory entries including a directory entry for each title. Each directory entry is a list of subchunk location entries in which each subchunk location entry includes a storage processor node identifier, a disk drive identifier, and a logical address for locating and accessing each subchunk of each title.

Abstract: A computer system of a federation coupled to a network including a server having an internal address associated with a first subnet and a network abstraction and isolation layer rules-based federation and masquerading (NAIL RBFM) interface that interfaces the server with the network. The NAIL RBFM interface transforms the internal address between the first subnet and a second subnet for intra-federation communications. The NAIL RBFM interface performs transform and inverse transform operations to convert between internal and external addresses of intra-federation network traffic. The operations may be performed on source and destination addresses, and may be configured in any of several manners, such as modifying at least one bit of an address, replacing at least one octet of an IP address, substituting a prefix of an address, replacing an entire address, etc.

Abstract: A variable area trim tab which is adjustable to control its effective area of the trim tab for use on boats having any of several propulsion methods. Area control is used to vary the effective lift area of the trim tab and to control the water flowing to, or flooding, the propeller. Flood doors and flood gates may be water blocking style, or water passing style to control water flow to the propeller. Area control and flood control components are also used as propeller guards, or propeller screens. Tunnel propellers use sliding and hinged tunnel closures to control water flow to the propeller. Sliding closures serve as propeller guards when the propeller is in the raised position. Side inlet water flow pipes allow water to fill propeller tunnels and serve as a side thruster propeller housing.

Abstract: A frequency control circuit including a controlled oscillator and an amplifier circuit is disclosed for providing a clock signal to a switched capacitor circuit which divides an input voltage to provide an output voltage. The controlled oscillator has a frequency control input receiving a frequency control signal and an output for providing the clock signal at a frequency based on the frequency control signal. The amplifier circuit has an input for receiving the output voltage and an output providing the frequency control signal based on droop of the output voltage. In one embodiment, the amplifier circuit adjusts the frequency control signal to optimize efficiency of the switched capacitor circuit over a voltage range of the output voltage, which changes based on load level.

Abstract: A mixing module includes a plurality of switched sample modules operably for generating a corresponding plurality of samples of an analog input signal in response to a control signal. A control module generates a mixing sequence and a control signal based on the mixing sequence, the control signal including a sequence of sample positions at a sampling clock rate and a sequence of scale factors, the sequence of scale factors based on an oscillation, wherein the sampling clock has a sample period and wherein the sequence of sample positions repeats at a sample position period greater than a sample interval, the sample interval equal to the sample period times the number of the plurality of switched sample circuits.

Abstract: A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response interface. The request interface provides a request via the request signals for a data transaction in which the request specifies a selected burst order. The response interface stores data received via the data signals into the cache memory according to the selected burst order. The request interface may specify the selected burst order by configuring a field of a request packet during a request phase of the data transaction. The selected burst order may selected from any of several different data transaction orderings, including an interleaved order, a linear order, a nibble linear order and a custom order. The microprocessor may further include instruction logic which provides an instruction to the bus interface logic specifying the selected burst order.

Abstract: A server cloud manager (SCM) for controlling logical servers and physical resources that form a virtualized logical server cloud. The SCM includes multiple core components and one or more interface components. The core components serve as a shared foundation to collectively manage events, validate and authorize server cloud users and agents, enforce predetermined requirements and rules and store operation data. The one or more interface components enable communication with external entities and includes an SCM proxy manager that enables communication with one or more SCMs of other server clouds. A server cloud system including a first server cloud that includes a first server cloud manager (SCM) and a first logical server, and a second server cloud that includes a second SCM. The first and second SCMs are configured to cooperate to manage operation of the first logical server.

Abstract: An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the first output node. A clock distribution system including multiple uniform adjustable buffers coupled between at least one root node and multiple destination nodes, where each uniform adjustable buffer is adjustable between a minimum delay and a maximum delay.

Abstract: A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle, asserting, by the bus agent, a target ready signal for one clock cycle in response to the write cycle during a first clock cycle of a data transfer phase of a prior write cycle or during a second clock cycle of a data transfer phase of a prior read cycle, asserting, by the bus agent, response signals in a next clock cycle following the clock cycle in which the target ready signal is asserted, asserting, by a processor, a data busy signal for the write cycle in the next clock cycle following the clock cycle in which the response signals are asserted, and asserting, by the processor, data for the write cycle when the data busy signal is asserted.

Abstract: A microprocessor interface system including a system bus with a bus clock and a quad-pumped address signal group, and including multiple devices coupled to the system bus. Each device is configured to perform a quad-pumped transaction on the system bus in which multiple request packets are sequentially transferred via the address signal group during each of multiple phases of one cycle of the bus clock. The devices may include at least one microprocessor and one or more bus agents. In one embodiment, the first address data is multiplexed onto the address signal group during first and second request packets during a first phase of the bus clock cycle, and the second address data is multiplexed onto the address signal group during third and fourth request packets during a second phase of the bus clock cycle.

Abstract: An integrated regulator and charging system including a DC/DC converter, a P-channel device, a battery system and a system/charger controller. The DC/DC converter converts an input voltage to a regulated voltage on a system bus. The battery system includes a rechargeable battery and a current sense device coupled in series between the drain of the P-channel device and ground, where the source of the P-channel device is coupled to the system bus. The system charger/controller regulates the system bus at a minimum voltage level when the battery voltage is below the minimum voltage level, such as a deeply discharged battery. The system charger/controller also regulates charge current through the battery when its voltage is between the minimum voltage level and a maximum voltage level and regulates the system bus at the maximum voltage level when the battery voltage is at the maximum voltage level.

Abstract: A PWM control circuit for a voltage regulator including a compensation network, a ramp generator providing a ramp voltage, an offset adjust circuit and a comparator circuit. The compensation network senses the output voltage, receives a reference voltage, and outputs a compensation voltage. The offset adjust circuit adjusts a selected one of the ramp voltage and the compensation voltage based on the reference voltage. The comparator circuit compares the compensation voltage with the ramp voltage and provides a PWM signal for controlling the output voltage. The offset adjust circuit may generate an offset voltage based on the reference voltage and a gain G of the voltage regulator. The offset adjust circuit may subtract the offset voltage from either the ramp voltage or the compensation voltage to provide an adjusted voltage to the comparator circuit.

Abstract: A controllable oscillator includes an output oscillation adjust module operably coupled to an oscillator for producing an effective output oscillation based on an oscillation control signal. The output oscillation adjust module includes an output select block that produces the effective output oscillation from a sequence of selected taps from the plurality of taps of the oscillator. A tap adjust control generator, responsive to the oscillation control signal generates a sequence of tap adjust control signals that command the output select block to select the sequence of selected taps from the plurality of taps. The tap adjust control generator includes an integrator having an integrator output, responsive to the oscillation control signal and a modulo(x) module for producing the sequence of tap adjust control signals based on the integrator output.