Abstract: A method of patterning and fabricating poled dielectric microstructures in dielectric materials comprising the following steps. A poled dielectric microstructure within a dielectric material is provided. The poled dielectric microstructure is then segmented into a plurality of independent sub-structures. The poled dielectric microstructures are then fabricated within each of the plurality of independent sub-structures. Additional processes and a novel poling setup for improving and implementing this patterning and fabrication method are also disclosed.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: A floating gate pixel is described which is formed by forming an N well in a P type silicon substrate. A P well is formed in the N well A gate is formed over a thin gate oxide, about 25 Angstroms thickness, such that the gate is directly over part of the P well and part of the N well. A P+ contact in the P well allows connection to a reset voltage source, usually through a reset transistor, to reset the pixel. The pixel is reset by setting the potential between the P well and the substrate, which is usually held at ground potential. When the pixel is reset tunneling current through the thin gate oxide sets the voltage of the floating gate. During the charge integration cycle an input signal to the pixel, such as a light signal, changes the potential of the pixel. After the charge integration cycle the tunneling current through the gate oxide changes the potential of the floating gate by an amount related to the input signal to the pixel.

Abstract: A method for forming a highly activated ultra shallow ion implanted semiconductive elements for use in sub-tenth micron MOSFET technology is described. A key feature of the method is the ability to activate the implanted impurity to a highly active state without permitting the dopant to diffuse further to deepen the junction. A selected single crystalline silicon active region is first amorphized by implanting a heavy ion such as silicon or germanium. A semiconductive impurity for example boron is then implanted and activated by pulsed laser annealing whereby the pulse fluence, frequency, and duration are chosen to maintain the amorphized region just below it's melting temperature. It is found that just below the melting temperature there is sufficient local ion mobility to secure the dopant into active positions within the silicon matrix to achieve a high degree of activation with essentially no change in concentration profile.

Abstract: The present invention provides a method and an apparatus for DRAM refresh with different frequencies of refresh for active and standby mode. In addition, this invention utilizes different refresh frequencies during active and standby modes to optimize power dissipation and DRAM data integrity. The refresh frequency during active mode is higher than said refresh frequency during standby mode. The refresh frequency during active mode is higher than the prior art refresh frequency during active mode. The refresh frequency during standby mode is lower than the prior art refresh frequency during standby mode. The higher active mode refresh frequency allows the faster restoration of cell data, which is degraded by capacitive discharge coupling through the selection of adjacent word lines. The low standby mode refresh frequency provides a lower standby power dissipation which compensates for the higher active mode power dissipation caused by the higher active mode refresh frequency.

Abstract: In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

Abstract: We disclose a technique to generate stretched solder columns (bumps) at the wafer level, suitable for wafer level packaging. This is accomplished through use of using two wafers—the standard (functional) wafer that contains the integrated circuits and a master (dummy) wafer on whose surface is provided an array of solder bumps that is the mirror image of that on the functional wafer. After suitable alignment, both sets of solder bumps are melted and then slowly brought together till they merge. Then, as they cool, they are slowly pulled apart thereby stretching the merged solder columns. Once the latter have fully solidified, they are separated from the master wafer only.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: A feedback image rejection downconversion system is described, which can be used in low IF receivers with good performance and completely integrated. In the forward path of the system, quadrature mixers and complex filters are used for frequency downconversion and separation of the RF signal from the image signal. In the feedback path, a correlator, a gain mismatch estimator and two VGAs have been used to detect, estimate and compensate the amplitude and phase mismatch between the forward I and Q path signals. The whole system is self-tuned and can operate in both closed and open loop mode. A very high and robust image rejection ratio (over 60 dB) has been achieved.

Abstract: An imaging method and system that flexibly accesses light sensor elements and processes imaging signals. The imaging system comprises an array of pixel sensor cells, an array controller and a readout control circuit.

Abstract: Nano-oxide based current-perpendicular-to-plane (CPP) magnetoresistive (MR) sensor stacks are provided, together with methods for forming such stacks. Such stacks have increased resistance and enhanced magnetoresistive properties relative to CPP stacks made entirely of metallic layers. Said enhanced properties are provided by the insertion of magnetic nano-oxide layers between ferromagnetic layers and non-magnetic spacer layers, whereby said nano-oxide layers increase resistance and exhibit spin filtering properties. CPP sensor stacks of various types are provided, all having nano-oxide layers formed therein, including the spin-valve type and the synthetic antiferromagnetic pinned layer spin-valve type. Said stacks can also be formed upon each other to provide laminated stacks of different types.

Abstract: A high performance specular free layer bottom spin valve is disclosed. This structure made up the following layers: NiCr/MnPt/CoFe/Ru/CoFe/Cu/free layer/Cu/Ta or TaO/Al2O3. A key feature is that the free layer is made of a very thin CoFe/NiFe composite layer. Experimental data confirming the effectiveness of this structure is provided, together with a method for manufacturing it and, additionally, its longitudinal bias leads.

Abstract: A method for forming a trimmed upper pole piece for a magnetic write head, said pole piece having a uniform width above and below a write gap layer. Prior art methods of trimming pole pieces to a final width using ion-beam etches produce pole pieces with thickness differentials due to the etch resistant nature of the alumina write-gap filling material. The present method uses NiCr, NiFeCr or Ru as write gap filling materials which have an etch rate which is substantially equal to the etch rate of the other layers forming the pole piece and are highly corrosion resistant.

Abstract: A method of forming a waveguide comprising the following steps. A structure is provided. An underclad layer is formed over the structure and a core layer is formed over the underclad layer. Patterning: the core layer to form the waveguide; and partially into the underclad layer, forming an overetched underclad layer having a projection underneath the waveguide. The waveguide having stress gradients and the overetched underclad layer having stress gradients.

Abstract: A lapping guide system and method for lapping a merged read/write head are disclosed. The resistance RRE of a first ELG near the sensor in the read head is correlated to the resistance RWE of a second ELG and to the width of a first optical lapping guide (OLG) near the neck region of the write head. As the lapping progresses, RWE and RRE increase and the OLG width along the lapping plane increases. Thus, an OLG width and a RWE corresponding to a target neck height or throat height and a RRE corresponding to a target stripe height are determined. A lapping plane is actively tilted to enable write head dimensions to be independently controlled on a per wafer or per row basis. The first OLG is a triangular feature with one side parallel to the lapping plane and the other two sides converging near the lapping plane.

Abstract: Methods and structures to reduce in semiconductor packages the length of critical electrical connections between bond pads on one or multiple semiconductor chips and wire landing pads on a substrate have been achieved. An electrical connection becomes critical if high current, high speed or radio frequency signals have to be transported. Moving the wire landing pads of critical connections on the substrate closer to the semiconductor chip utilizing unpopulated spaces of an array grid design reduces the length of said wires. This could be a ball grid array (BGA) or any other kind of grid array. Said methods and structures invented are applicable to single-chip modules and to multi-chip modules. The design of the grid array has to be modified to provide free spaces for the wire landing pads of critical electrical connections within the grid array close to the semiconductor chip as required by the design rules. The design change can be done without increasing the number of solder balls or solder pins, etc.

Abstract: Currently, the shield-to-shield separation of a spin valve head cannot be below about 800 ?, mainly due to sensor-to-lead shorting problems. This problem has now been overcome by inserting a high permeability, high resistivity, thin film shield on the top or bottom (or both) sides of the spin valve sensor. A permeability greater than about 500 is required together with a resistivity about 5 times greater than that of the free layer and an MrT value for the thin film shield that is 4 times greater than that of the free layer. Five embodiments of the invention are described.

Abstract: Disclosed is a method of making a SVGMR sensor element. In the first embodiment a buffer layer is formed between a seed layer and a ferromagnetic (FM) free layer, the buffer layer being composed of alpha-Fe2O3 having a crystal lattice constant that is close to the FM free layer's crystal constant and has the same crystal structure. The metal oxide buffer layer enhances the specular scattering. In the second embodiment, a high conductivity layer (HCL) is formed over the buffer layer to create a spin filter-SVGMR. The HCL layer enhances the GMR ratio of the spin filter SVGMR. The third embodiment include a pinned FM layer comprising a three layer structure of a lower AP layer, a space layer (e.g., Ru) and an upper AP layer.

Abstract: A high radiation efficiency antenna system in a package is achieved by the provision of a Dielectric Resonator Package. A Dielectric resonator package comprises a dielectric body of the package forming a dielectric resonator that resonates at radio frequency and a feed substrate having an upper and a lower surface, a feed structure formed on the upper surface of the feed substrate, and RF circuitry mounted on the lower surface of the feed substrate. The feed substrate is attached to the dielectric body of the package from the side of the feed structure.

Abstract: A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species.