Abstract: A circuit and method are described which suppresses reset noise in active pixel sensor arrays. A circuit having a number of N? wells formed in a P? silicon epitaxial layer or a number of P? wells formed in an N? silicon epitaxial layer is provided. A pixel is formed in each of the wells so that each of the wells is surrounded by silicon of the opposite polarity and an array of pixels is formed. Means are provided for selectively combining or binning adjacent N? or P? wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated. The reset is accomplished using a PMOS transistor formed in each N? well or an NMOS transistor formed in each P? well. The selective binning is accomplished using NMOS or PMOS transistors formed in the region between adjacent wells.

Abstract: The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is prevented by at least two barrier layers. One or two barrier layers are located at the interface between the connector and the insulating layer while another barrier layer comprises conductive material and covers the upper surface of the connector. When a second damascene connector is formed above the first connector the conductive barrier layer facilitates good contact between the two connectors. It also acts as an etch stop layer during the formation of the second connector. A process for manufacturing this structure is also described. It involves over-filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing.

Abstract: A data storage device (10) includes a stator (20), a rotor (40), a disk (80), and a clamp (60) attaching the disk to the rotor. The rotor includes a hub (48) forming a shoulder (57) at a top portion thereof. A recess (56) is defined in the top portion of the hub and surrounded by the shoulder. An outer diameter of the recess is equal to or larger than a diameter of a central opening (82) of the disk. The disk is seated on the shoulder of the hub. The clamp includes a bottom fixing part (62) fixedly attached to the hub in the recess, a cylindrical wall (64) abutting an inside of the shoulder and the disk in the central opening, and a pressing part (66) extending through the central opening of the disk and pressing on the disk thereby ensuring that the disk can rotate with the rotor.

Abstract: A bit line decoding circuit for accessing an array of two-bit memory cells. Two adjacent memory cells can be accessed by applying appropriate voltages to the terminals of the cells. A bit line decoder selects plural bit lines in the memory array and provides paths to apply or receive the voltages to or from the selected bit lines. In one embodiment, shared control gates of pass transistors which function as the bit line selection in a bit line deocder provides reduction in the number of control signals. Functions of applying a voltage for neighbor effect reduction and of providing a path for a reference voltage are also implemented in further embodiments.

Abstract: A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.

Abstract: A method of filling an STI feature with a dielectric material using a HDP CVD technique is described. By omitting an inert carrier gas like argon in the first CVD step, a small keyhole in a SiO2 layer is formed near the top of the trench. A sputter etch step in the same CVD chamber then removes dielectric material above the keyhole. A second CVD step completely fills the STI trench which is free of voids and forms a layer above the adjacent nitride layer. The nitride layer serves as an etch stop during a CMP step to lower the level of dielectric material until it is coplanar with the nitride layer. The method is low cost since all deposition and sputter etch steps are performed in an existing CVD tool and the same tool is useful in forming trenches of various sizes ranging from below 0.13 micron to above 0.25 micron.

Abstract: A flat panel antenna, monopole or dipole, formed from a conductive loaded resin-based material containing micron conductive powders or micron conductive fibers to provide conductivity. The monopole antenna has an antenna element having an outer periphery with a length equal to an integral multiple of a quarter wavelength of the desired center frequency of the antenna. A bobbin, also formed of the conductive loaded resin-based material, and is attached to the antenna element by connection elements. A coil of conductive wire, having two ends connected to a coaxial cable, is wound around the bobbin. The coaxial cable can deliver power to a radiating antenna or extract power from a receiving antenna. The dipole antenna has first and second antenna elements both formed of conductive loaded resin-based material. The peripheries of the first and second antenna elements have lengths equal to an integral multiple of a quarter wavelength of a first and second frequency.

Abstract: A new method and apparatus is provided that assures constant fluid flow of the fluid that is entered into a semiconductor device processing tank or container. A flow meter is set to a particular flow rate; the fluid that comes from the POU is routed through the flow meter. The fluid passes through a flow meter into a processing tank. The fluid is allowed to fill the container up to an overflow point of the container. An overflow basin is provided into which the overflowing fluid is routed from where the fluid is drained into a fluid reclaim vessel. The overflow is detected by a sensor, the sensor activates an overflow relieve valve that is mounted in the bottom of the container. The overflow relieve valve is opened and drains fluid from the container thus counteracting the overflow of the fluid into the overflow basin. The interaction between the overflow detector and the overflow relieve valve assures a constant rate of supply of the fluid to the processing tank or container.

Abstract: A circuit where the same amplifiers and the same volume adjustment circuitry are used for the ringer mode as well as for the audio mode of a mobile phone is achieved. The volume adjustment in the audio and ringer mode is provided by a precise amplitude setting via the gain control stages of an inverting voltage amplifier used in a bridge circuit through a current-voltage conversion. This volume adjustment circuit avoids the high power dissipation of a volume control through pulse width modulation (PWM) and avoids the risk of over-and undershooting of the amplifier's output signal due to a high slew rate in combination with the inductance of the loudspeaker. The current-voltage conversion is performed by a series of resistors activated by a series of correspondent switches. High impedance current less sense paths are eliminating the parasitic effect of the resistance of low cost standard switches to adjust the volume of the loudspeaker in the audio and the ringer mode.

Abstract: Low cost antennas formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises conductor fibers or conductor particles in a resin or plastic host wherein the ratio of the weight of the conductor fibers or conductor particles to the weight of the resin or plastic host is between about 0.20 and 0.40. The conductive fibers can be stainless steel, nickel, copper, silver, or the like. The antenna elements can be formed using methods such as injection molding or extrusion. Virtually any antenna fabricated by conventional means such as wire, strip-line, printed circuit boards, or the like can be fabricated using the conductive loaded resin-based materials. The conductive loaded resin-based material used to form the antenna elements can be in the form of a thin flexible woven fabric which can readily cut to the desired shape.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: A multi-segmented planar antenna with a built in ground plane and method of forming the antenna are described. The antenna elements are formed on a layer of first dielectric having conducting material on both the first and second sides of the layer of first dielectric, such as a printed circuit board. Antenna elements are formed on both sides of the layer of first dielectric using selective etching of the conducting material. Two antenna elements are generally rectangular separated by a narrow gap and electrically connected by two shorting strips across the gap. Two antenna elements are long and narrow wherein the length of each is an integral multiple of a quarter wavelength of the operating frequencies of the antenna A layer of second dielectric is placed between the layer of first dielectric having the antenna elements and a ground plane. The antenna can be fully encapsulated in a plastic encapsulation material.

Abstract: A method for preventing electrostatic discharge (ESD) damage in the head-suspension assembly (HSA) construction process. The method teaches the formation of a novel GMR magnetic recording head on a conductive slider substrate, the GMR head being electrically connected to the substrate and its conducting leads having balanced resistances between the leads and the substrate. By establishing an electrical connection between the GMR head and the slider substrate, the entire HSA can be grounded during its construction. By also grounding any nearby conducting elements that could inadvertently contact the HSA or its parts, no accumulated tribocharges can discharge through the sensitive GMR sensor element.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N? well. The N? well is in a P? type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N? well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N? well potential so that they remain reverse biased with respect to the N? well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N? well forms a second gate for the dual gate PMOS transistor since the potential of the N? well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible.

Abstract: A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract: A circuit to independently control rise and fall delay edge timing of a signal is achieved. The circuit comprises, first, a first delay element and a second delay element. Each of the delay elements has an input and an output. Each of the inputs is coupled to a common, input signal. Next, an AND function, having two inputs and one output, is used. One of the AND inputs is coupled to the input signal, and another of the AND inputs is coupled to the first delay element output. The AND function output comprises a rise-delayed signal having a controlled rising edge delay between a rising edge of the input signal and a rising edge of the rise-delay signal. Finally, an OR function, having two inputs and one output, is used. One of the OR inputs is coupled to the input signal, and another of the OR inputs is coupled to the second delay element output.

Abstract: A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop.

Abstract: Patterned, longitudinally and transversely antiferromagnetically exchange biased GMR sensors are provided which have narrow effective trackwidths and reduced side reading. The exchange biasing significantly reduces signals produced by the portion of the ferromagnetic free layer that is underneath the conducting leads while still providing a strong pinning field to maintain sensor stability. In the case of the transversely biased sensor, the magnetization of the free and biasing layers in the same direction as the pinned layer simplifies the fabrication process and permits the formation of thinner leads by eliminating the necessity for current shunting.