Abstract: A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconductor substrate not covered by the gate structure or by composite insulator spacers located on the sides of the gate structure. Selective removal of an overlying insulator component of the composite insulator spacer allows a subsequent pocket implant region to be formed in an area of the semiconductor substrate directly underlying a horizontal portion of a remaining L shaped insulator spacer component. The location of the pocket region, formed butting only the top portions of the sides of the heavily doped source/drain region, reduces the risk of punch through current while limiting the impact of junction capacitance.

Abstract: A circuit and a method to measure continuously the resistance of variable resistors in series as e.g. potentiometers within a sensor, used for e.g. a joystick, has been achieved. The voltage across said sensor comprising any number of variable resistors is stabilized. A constant current source is providing a minimum current through said sensor. A variable current source is used to zoom variations of current through the sensor caused by variations of resistance of the sensor. Said variable current is mirrored and by measuring the voltage across a shunt resistor the total resistance of the sensor is identified. Using ports between each of the resistors, voltages can be measured representing the resistance of each of the variable resistors using known equations of voltage dividers. Any number of variable resistors can be used in the circuit invented.

Abstract: A method and apparatus for dynamically balancing the loading of data storage facilities is described. A listing is acquired of locations and loading of all segments of a requested data object including all copies of the segments of the requested data object. Those storage devices containing copies of each segment of the data object having a least loading is selected. If the loading of the storage devices is greater than the maximum loading for the storage devices, the segment is designated to be copied. The presence of all segments of the requested data object is determined. If there are missing segments of the requested data object, each of those missing segments is assigned a file identification and file location, such that those missing segments are assigned to data storage devices having the least loading. The missing segments are retrieved from a back-up storage device.

Abstract: The present invention relates to display adjustment and balance methods for liquid crystal displays, LCDs. A wide-range display position adjustment method is described. Compared with the prior art liquid crystal display controllers, the embodiments of this invention are not limited by the width of the vertical and horizontal front and back porch regions of the timing diagrams. These porch values are a function of the display chip technology. The display location control of this invention is independent of the limits of the front and back porch times. The embodiments of this invention facilitate the design of a display position control circuit which allows the image display to be rolled around anywhere on the panel.

Abstract: A harvester and method for harvesting aquatic algae or floating vegetation in shallow areas of water bodies, such as lakes is described. The harvester is manually operated. The harvester moves on hollow wheels that are capable of adjusting the buoyancy of the harvester by adding or subtracting water/air into the hollow wheels. The aquatic algae or floating vegetation is collected on the harvester, removed from the harvester, dewatered and used for compost in garden and agricultural activities.

Abstract: A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) are described. Serial write access by means of a serial interface and read access with a read strobe from an independent read device are generated asynchronously. Prerequisites for the implementation are: firstly, use of a serial interface providing a serial clock signal; secondly, write access to SPRAM has to occur at the end of serial transmission; thirdly, a write strobe impulse has to be short compared to the original read strobe. Energy saving is achieved by guaranteeing only one regular read strobe, even when multiple write accesses occur during one read access. The read strobe signal can therefore be used also for control of an LCD backplane counter.

Abstract: A magnetic read/write head and slider assembly and method for forming the magnetic read/write head and slider assembly, wherein the assembly has improved heat spreading and dissipation properties and exhibits significantly reduced thermal protrusion during operation. The method consists of the formation of a heat sink layer on a portion of either the upper pole yoke or the lower magnetic pole of the writer.

Abstract: An improved charge pump circuit is provided using a triple-well structure where the charge pump circuit has a plurality of stages containing N-channel MOSFET devices in which each stage is contained in a P-well within a Deep N-well residing on a P-substrate. Each pump stage is formed in its own P-well and the pumping stages are serially connected from power supply source to the output terminal. Each pumping stage includes a charge transfer device, a first auxiliary device to precharge the gate of the charge transfer device with a voltage from the previous stage, and a second auxiliary device to switch coupling between the charge transfer device and its substrate region to reduce the body effect and increases the capacitive boosting effect. The multiple stages of circuitry are clocked from either a four-phase clock or a two-phase clock.

Abstract: A circuit and a method for an effective way to customize the display driver software of any type of LCD-display and any type of LCD-driver chip used in an LCD display system is achieved. This is important in a multiple sourcing environment where LCD driver chips and LCD modules from different vendors are used in LCD display systems. This is accomplished through identification and registration of the information relevant for the said software customization by storing said information in an LCD module identification register. A microprocessor controlling the LCD display system is reading this identification register and providing the software customization elements specific to the LCD-driver chip and to the LCD-module during an initialization step of the system.

Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top corners of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.

Abstract: A data storage device (10) includes a housing enclosing a clean room chamber (CR), a stator (20), a rotor (40), and a plurality of data storage disks (60). The housing includes an upper partition (12) and a lower partition (14). The stator includes a plurality of stator laminations (22) each having a winding (24) wound therearound, and a shaft (30) having opposite ends fixed with the upper partition and the lower partition. The rotor includes a hub (44), a tube (42) fixed in the hub, and a magnet (46) surrounded by the stator laminations. The hub includes a radially extending shoulder (45) for supporting the disks thereon. The tube surrounds the shaft, with a pair of bearings (50) rotatably connecting the tube to the shaft. A clamp (80) is secured on the hub, and presses on a top one of the disks to mount the disks to the hub.

Abstract: A CMOS pixel responsive to different colors of optical radiation without the use of color filters is described. A deep N well is formed in a P type silicon substrate. An N well is then formed at the outer periphery of the deep N well to form a P well within an N well structure. Two N+ regions are formed in the P well and at least one P+ region is formed in the N well. A layer of gate oxide and a polysilicon electrode is then formed over one of the N+ regions. The PN junction between the deep N well and the P type silicon substrate is responsive to red light. The PN junction between the deep N well and the P well is responsive to red light. The PN junction between the P well and the N+ region which is not covered by polysilicon and the PN junction formed by the N well and the P+ region are responsive to green or blue light. The PN junction formed by the junction between the P well and the N+ region which is covered by polysilicon is responsive to green light.

Abstract: In this invention a coating of unexposed photoresist is used to protect from semiconductor processing the area immediately above a zero layer alignment mark used for a wafer stepper alignment. The entire surface of a wafer is coated with photoresist and all shot sites on the surface of a wafer including those containing the zero layer alignment marks are exposed with circuit patterns. Before the exposed areas of photoresist are removed, a protective coating of unexposed photoresist is applied to the surface of the wafer immediately above the alignment marks but within the boundaries of the shot site. The wafer is processed in the areas outside of the protective coating of photoresist including the shot site containing alignment marks. The area under the protective coating is not processed. This maintains a clear and concise view of the alignment marks. The area beyond the protective coating is processed along with the other shot sites.

Abstract: A process for characterizing defects in semiconductors or insulators using a zero-bias thermally stimulated current technique wherein parasitic current is eliminated by the use of a novel ZBTSC apparatus that eliminates temperature gradient across a sample is described. The novel ZBTSC apparatus comprises a cold finger on a cyrostat. A sample holder is attached to the cold finger. A probe holder is attached to the cold finger. A probe is attached to the probe holder. A feedback temperature control keeps the probe and the cold finger at the same temperature. Alternatively, the sample holder may be attached to a first cold finger and the probe holder attached to a second cold finger. Feedback temperature controls for each cold finger are programed such that their temperatures are kept the same. The improved zero-bias thermally stimulated current technique of the invention comprises mounting a sample on the sample holder of the novel ZBTSC apparatus.

Abstract: A method for forming a bottom spin valve sensor having a synthetic antiferromagnetic pinned (SyAP) layer, antiferromagnetically coupled to a pinning layer, in which one of the layers of the SyAP is formed as a three layer lamination that contains a specularly reflecting oxide layer of FeTaO. The sensor formed according to this method has an extremely high GMR ratio and exhibits good pinning strength.

Abstract: As feature sizes approach 0.1 ?m or smaller, reduction of line edge roughness (LER) becomes increasingly important. Significant reductions in edge roughness have been achieved by applying a second Ebeam exposure after the initial one that is used to define the pattern. After this second blanket exposure a longer heat treatment and a stronger development process than before are used. In addition to reducing edge roughness the disclosed treatment allows the CD to be reduced under tight control since the amount of CD reduction is proportional to the second Ebeam dosage.

Abstract: An improved and new process for fabricating self-aligned metal barriers by atomic layer deposition, ALD, capable of producing extremely thin, uniform, and conformal metal barrier films, selectively depositing on copper, not on silicon dioxide interlevel dielectric, in multi-layer dual damascene trench/via processing. Silicon nitride is presently used as a insulating copper barrier. However, silicon nitride has a relatively high dielectric constraint, which deteriorates ICs with increased RC delay. Copper metal barriers of niobium and tantalum have been deposited by atomic layer deposition on copper. With high deposition selectivity, the barrier metal is only deposited over copper, not on silicon dioxide, which eliminates the need of an insulating barrier of silicon nitride.

Abstract: An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation transistor has gate, drain, source, and channel. The source is defined as a cell source line. Finally, a floating gate transistor has control gate, floating gate, drain, source, and channel. The drains and sources of each transistor comprise a diffusion layer in the substrate. The channels of each transistor comprise the substrate. The floating gate transistor drain is coupled to the selection transistor source. The floating gate transistor source is coupled to the isolation transistor drain. The device is programmed and erased by charge tunneling between the floating gate and the floating gate transistor channel. The device may further comprise an isolation well underlying the diffusion layer. A two transistor EEPROM cell is disclosed. Several array architectures using the EEPROM cell are disclosed.

Abstract: A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

Abstract: An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.