Patents Represented by Attorney, Agent or Law Firm Gerald E. Linden
  • Patent number: 5413814
    Abstract: Articles, such as plastic parts, having the appearance of a naturally-occurring material such as wood or leather are formed by the techniques of (1) providing a plurality of grooves in a surface of the article, (2) applying a surfactant to the surface of the article, and (3) applying one or more color solutions to the surface of the article. The article may be a solid substrate, a part or a film. A topcoat is preferably applied to the surface of the article. The techniques include controlling movement of an applicator implement for applying the surfactant and color solutions to the surface of the substrate, and controlling movement of a saturator tool for modifying and synthesizing the surfactant and color solutions on the surface of the part and permeating the surfactant and color solutions into the plurality of grooves.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: May 9, 1995
    Inventors: Robert L. Bowen, Manuel C. Turchan
  • Patent number: 5395288
    Abstract: Improvements and alternate embodiments for two-sided, self-replicating forms are described, Form sets having two single sheets, each sheet delineated into two panels, making three two-sided copies of a two-sided original are described with fully-coated carbonless coatings and with patterned carbonless coatings. A form set having two single sheets, each sheet delineated into two panels, making four two-sided copies, two of which have original writing on one surface, is described. A single sheet form, delineated into two panels, making two two-sided copies, each of which has original writing on one surface, is described. A single sheet form, delineated into an original and a copy panel, making a two-sided copy of an original having original writing on both surfaces is described. A form set having a single sheet delineated into an original un-coated panel and a CF-coated copy panel, and employing a separate CB-coated image-transferring sheet is described.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: March 7, 1995
    Inventors: Gerald E. Linden, Keith E. Schubert
  • Patent number: 5394747
    Abstract: As a particularly simple and compact metering apparatus for the continuous gravimetric metering of pourable material it is suggested to form a rotor (5) driven about a vertical rotational axis (4) and supported about a horizontal pivot axis (7) as a disk-type smooth-plane measuring disk and to arrange in the discharge region (6) a stripping-off element (10) extending over the radius of the measuring disk (9). In a preferred embodiment of the invention the pivot axis (7) extends - seen in plan view - centrally through the charge tunnel (3) and the stripping-off element (10).
    Type: Grant
    Filed: July 2, 1993
    Date of Patent: March 7, 1995
    Assignee: Pfister GmbH
    Inventor: Hans W. Hafner
  • Patent number: 5393265
    Abstract: Improvements to self-replicating duplex forms are disclosed. Generally, a single sheet of paper is divided into original and copy panels by fold line, and carbonless coatings are applied to the panels so that information entered on the two, front and back surfaces of the original panel are reproduced on the two surfaces of the copy panel.(Group 1) An endorsable carbonless CB coating is applied to the original panel, either at the mill or on-press. A carbonless CF coating is applied to the copy panel so that the coated copy panel is substantially the same thickness as the coated original panel. Specific areas for filling out information on the original panel are offset, from front-to-back, and methods of checking this offset are disclosed. The copy panel is tinted a dissimilar base color from the original panel.(Group 2) The original and copy panels can be formed separately, and joined into a single "virtual" sheet.(Group 3) The original and copy panels can be formed of a single sheet of CF C2S paper stock.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: February 28, 1995
    Inventors: Gerald E. Linden, Keith E. Schubert
  • Patent number: 5389556
    Abstract: A plurality of unsingulated dies on a wafer may be individually powered up using various "electronic mechanisms" on the wafer, and connecting the electronic mechanisms to the individual dies by conductive lines on the wafer. The electronic mechanisms are capable of powering-up a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively power up the dies.
    Type: Grant
    Filed: July 2, 1992
    Date of Patent: February 14, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, James Koford
  • Patent number: 5362356
    Abstract: A passive, in-line method of monitoring film removal (or deposition) during plasma etching (or deposition) based on interference phenomena is disclosed. Plasma emission intensity is monitored at a selected wavelength, without additional illuminating apparatus, and variations in plasma emission intensity are correlated to remaining film thickness, etch rate and uniformity, and etch selectivity. The method is useful in conjunction with nitride island etch, polysilicon etch, oxide spacer etch, contact etch, etc. The method is also useful in determining a particular remaining film thickness (e.g., just prior to clearing) at which point the etch recipe can be changed from a high-rate, low selectivity etch to a low-rate, high-selectivity etch.
    Type: Grant
    Filed: January 14, 1992
    Date of Patent: November 8, 1994
    Assignee: LSI Logic Corporation
    Inventor: Philippe Schoenborn
  • Patent number: 5354706
    Abstract: A method for forming uniformly sized features, such as polysilicon lines or gates, or such as conductive lines, on a semi conductor wafer having a planar upper surface is described which minimizes variations in the critical dimensions of the features. The technique allows a substantially uniform overlying layer, such as photoresist, to be formed above the layer intended to contain the features. The method can be applied to forming isolation trenches around active areas on the semiconductor wafer, overfilling the trenches with an insulating material (e.g., oxide), polishing back the oxide to a planar surface, depositing a planar layer of a conductive material (e.g., poly), and depositing a planar layer of a photoresist. The planar layer of photoresist, being deposited over a planar layer of conductive material has substantially uniform thickness and correspondingly uniform reflectivity.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: October 11, 1994
    Assignee: LSI Logic Corporation
    Inventor: Roger Patrick
  • Patent number: 5347162
    Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of reflow solder joints between conductive bumps on the die and corresponding conductive bumps of the substrate. In one embodiment, conductive elements embedded in the preformed planar structures extend at least partially into the through holes, forming electrical connections with the corresponding solder joints. The conductive elements can be used to electrically connect one solder joint to another within the interposer, and/or may extend beyond an edge of the interposer to provide for electrical probing of or connection to the solder joints. In one embodiment, the conductive elements are extended outside of the preformed planar structure to form "pins" or leads of the flip-chip structure.
    Type: Grant
    Filed: August 12, 1993
    Date of Patent: September 13, 1994
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 5345310
    Abstract: Techniques for identifying and determining the orientation, magnitude, and direction of slip plane dislocations transecting semiconductor dies are described, whereby a four point alignment pattern is examined for "squareness" and size integrity. Lack of squareness or significant change in apparent size of various aspects of the alignment pattern indicate slip-plane dislocations. The magnitude, orientation and direction of the dislocations are determined geometrically from measurement of the alignment pattern. Various other aspects of the invention are directed to optimal alignment of a photolithographic mask to a die which has experienced a slip-plane dislocation, and to discrimination between slip-plane dislocation and die-site rotation.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: September 6, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5340978
    Abstract: A camera comprising various arrangements for employing optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements and methods of making same are discussed.
    Type: Grant
    Filed: April 21, 1993
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, David E. Sanders
  • Patent number: 5340011
    Abstract: In a semiconductor wire bonder, the need for frequently changing chucks and re-focusing optical equipment for each different die/package thickness combination is alleviated by providing an adjustable stop mechanism lifting the upward displacement of the die/package off of a carrier. The adjustable stop mechanism includes a first, stationary bracket having a leg extending towards a movable lifting member of the bonder, and a second bracket mounted to the movable lifting member. A set screw extending through the leg of the first bracket limits the upward movement of the movable member, and ensures that the front surface of a die being bonded is at an optimum position for bonding.
    Type: Grant
    Filed: December 9, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Antonio Sanchez
  • Patent number: 5340772
    Abstract: Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Patent number: 5341024
    Abstract: Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Patent number: 5339940
    Abstract: A piece of movable equipment is provided with a male docking bar (10) . An immovable piece of equipment is mounted to an immovable fixture which has a female docking bar (28). The female docking bar (28) has freedom to move in a first axis. The movable piece of equipment is brought into contact along a second, orthogonal axis to meet the immovable piece of equipment, at which point lugs (12) on the male docking bar mate with corresponding holes (30) on the female docking bar. The male locking bar can then be interlocked (16, 32) to the female docking bar. The movable piece of equipment can then further be moved along the first axis.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Alan Simms
  • Patent number: 5340771
    Abstract: Techniques for providing semiconductor packages capable of forming connections to "high I/O" semiconductor dies is described, wherein there are at least two distinct pluralities of conductive lines. Leadframe-type packages and substrate-based package embodiments are described.
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rostoker
  • Patent number: 5337614
    Abstract: A reliable, repeatable, well-characterized, safe technique for testing the mounting integrity of heat sinks adhered to semiconductor packages is disclosed. Generally, a semiconductor package is secured in a tensiometer, the heat sink is clamped and secured to the spindle of the tensiometer, and a stud-pull type test is conducted.
    Type: Grant
    Filed: August 20, 1992
    Date of Patent: August 16, 1994
    Assignee: LSI Logic Corporation
    Inventors: Xin H. Jiang, Scott Kirkman
  • Patent number: 5330883
    Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: July 19, 1994
    Assignee: LSI Logic Corporation
    Inventor: Mario Garza
  • Patent number: 5329157
    Abstract: A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: July 12, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Patent number: 5326427
    Abstract: A method of selectively etching titanium-containing materials without attacking aluminum or silicon dioxide is describe, wherein an atomic chlorine etching environment is generated using downstream techniques. Atomic chlorine in the absence of ion bombardment (as provided by downstream etching) etches titanium-containing materials such as titanium nitride without attacking silicon dioxide. In one embodiment of the invention, atomic chlorine is generated by the discharge of energy into molecular chlorine. In another embodiment of the invention, discharge of energy into a fluorine-containing gas causes the generation of atomic fluorine. Molecular chlorine is then added, creating a fluorine-chlorine exchange reaction which produces atomic chlorine. The presence of fluorine inhibits etching of aluminum, but does not impede the etching of titanium-containing materials.
    Type: Grant
    Filed: September 11, 1992
    Date of Patent: July 5, 1994
    Assignee: LSI Logic Corporation
    Inventor: Chris Jerbic
  • Patent number: 5325716
    Abstract: An apparatus for determining the pressure distribution along a limited distance comprises a plurality of pressure sensors arranged at predetermined distances to each other and connected to an evaluation circuit, the pressure sensors being arranged, in particular embedded, in/at a preferably round rope-type body of elastomeric material, the body being surrounded by a non-elastic, however in radial direction deformable cover in fixed connection thereto. The apparatus may be advantageously used as a filling level indicator in a bin or for various other purposes.
    Type: Grant
    Filed: February 7, 1992
    Date of Patent: July 5, 1994
    Assignee: Pfister Messtechnik GmbH
    Inventors: Hans W. Hafner, Gerhard Altmayer