Abstract: A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A tester stimulates the a device (DUT) with input patterns. DUT output patterns are communicated back to the tester, and are compared to simulation results. Failing outputs are identified. Working back from the failing output, suspect failing nodes are identified in a schematic editor. Through a layout database linked to the schematic editor, the position of each suspect failing node is identified. A probe and SEM are positioned at nodes suspected of causing the failure. Live waveforms generated by the probe are compared with simulated waveforms for the node, while the DUT is being re-exercised by the tester. In a windowed display environment, the user is provided with schematic, layout, SEM image, and live and simulated waveforms for the suspect node. Node after node are explored in this manner until the failing circuit element is identified. Documentation is provided by printing any and all of the windows.

Abstract: A conformal, substantially uniform thickness layer of photoresist is deposited on a semiconductor wafer by causing photoresist solids to "sediment" out of solution or suspension. Generally, the more conformal the layer, the more uniform the reflectance of the layer and the less variation in underlying feature critical dimension (cd). In order to accommodate possible resulting deviations in photoresist layer thickness causing undesirable reflectance nonuniformities (and cd variations), a top antireflective coating may be applied to the photoresist layer. In the case of a point-by-point lithography process, such as e-beam lithography, the thickness/reflectance variations can be mapped, and exposure doses adjusted accordingly.

Abstract: A contact structure is formed atop a semiconductor wafer at a level whereat it is desired to terminate polishing of a layer overlying the contact structure. When the contact structure becomes exposed to a polishing slurry, an electrical characteristic, such as resistance or impedance, is registered by measuring apparatus. In one embodiment, two or more contact structures are formed atop the wafer, vias are formed through the wafer, and the vias are filled, thereby providing a conductive path from the contact structures to the back side of the wafer. The measuring apparatus probes the filled vias on the back side of the wafer. A change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated. In another embodiment of the invention, one or more contact structures are formed atop the wafer. The measuring apparatus is connected to a probe in the polishing slurry, and to the wafer itself, such as to the back side of the wafer.

Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion 58 region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Abstract: A first, lower heat sink disposed immediately below and closely adjacent a semiconductor chip (die) in a semiconductor chip assembly is disclosed. The lower heat sink is a flat metallic or ceramic shim. A second, upper heat sink disposed immediately above and closely adjacent the top surface of the semiconductor device is disclosed. The upper heat sink may have a portion in contact with a passivation layer over the top surface of the semiconductor die (device). The second heat sink preferably has a flat surface forming an exterior surface of the semiconductor device assembly. In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications wherein the semiconductor chip assembly is mounted to a thermal mass.

Abstract: A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.

Abstract: A wide-dynamic range optical receiver amplifier is provided by using two separate amplifiers. The first amplifier is a low-impedance input, low-noise, high-gain amplifier, preferably a transresistance amplifier. An input resistor is chosen for the amplifier such that its resistance value is much greater than the input impedance of the first amplifier, resulting in insignificant change in input impedance when the first amplifier's output becomes saturated. A light-induced signal source is connected to the input resistor such that signal current from the light-induced signal source flows through the input resistor into the first amplifier input. A second high-input-impedance amplifier (preferably an FET-input buffer amp) is connected to receive the light induced signal source, either directly or through a resistive divider network.

Abstract: A digital filter device is for use in signal processing paths for parallel processing n series of input signals having a common sampling frequency f.sub.i and parallel delivering n series of output signals. Input signals of the n series are sequentially switched for delivery to a single FIR (finite-duration impulse response) filter which is commonly used in a time sharing manner so that the FIR filter is shared by the n series of signals. Use of time shared FIR filter allows for the construction of the digital filter device from a reduced number of elements. Also provided is a sampling frequency conversion apparatus using the digital filter. A MUSE (multiple sub-Nyquist subsampling encoding) decoder uses a single sampling frequency conversion apparatus for both still and motion picture signal processing paths in a time sharing manner.

Abstract: A laser light show device and method produces a surface projected or suspended holographic image, and includes multiple image projectors. One image projector provides the object image information representing the primary subject. For surface projections, additional background image projectors provide background image information generated using a wobbler plate-reflected beam diffracted through a spherical lens, a beam unidimensionally diffracted through a rotating cylindrical amorphic dipolyhedral lens, and a beam diffracted through multiple diffraction gratings. A suspended holographic image is produced by parabolically focusing multiple images projected onto a spherical image screen.

Abstract: A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or conductive epoxy through cutouts in the pad. In one embodiment, the cutouts extend into the pad from inner and outer edges thereof. In another embodiment, the cutouts are holes through the pad. A plurality, such as four, capacitors are conveniently disposed atop a corresponding plurality of pads, and are connected to a corresponding plurality of pairs of leads within the semiconductor device assembly. By positioning the capacitor(s) as closely to the semiconductor device as possible, the efficacy of the capacitor(s) is maximized. Method and apparatus are disclosed.

Abstract: At least one sidewall panel of a pizza box blank is provided with at least one removable punch-out section. For disposing of the assembled (inter-folded) pizza box, the punch-out section is removed, and the assembled box is folded in half to diminish a major dimension thereof. Additionally, a series of weakening lines are provided which allow the punched out sidewall panel to deform inwardly, into the assembled box, for further facilitating easy folding for disposal in a trash receptacle.

Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.

Abstract: A novel technique for increasing bond pad density is described whereby non-square bond pads are shaped, sized and oriented such that each bond pad closely conforms to the shape of the contact footprint made therewith and are aligns to the approach angle of the conductive line to which it is connected. A variation on the inventive technique provides for alternating, interleaved, complementary wedge-shaped bond pads which provide for high bond pad density while accommodating a wide range of approach angles.

Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Abstract: A fluid distribution head of this invention includes a chamber for fluid flow including a perforated plate. The perforated plate is internally supported by a structural support to avoid deformation of the plate.

Abstract: A computer system module includes a central processing unit (CPU), a floating-point accelerator (FPA), a read/write buffer (RWB), cache memory, a clock generator, buffers, and reset logic. The signal composition of the module includes: Configuration Buffer Enable (CfgEn); Page Write (PgWrt); Block Match (BlkMtch); Byte Write Mask (WrMsk); and Test Enable (TestEn). The layout of the various components on a printed circuit board (PCB) minimizes transmission line effects, such as transmission line delay (t.sub.D) and signal reflections, by keeping trace lengths as short as possible, and no line terminations are required. A heat sink (heat spreader) is provided for critical semiconductor devices, such as the CPU and the FPA. The heat sink includes a broad flat section and a button protruding from a surface thereof. An unpackaged device is mounted to the button, with a thermally and electrically conductive adhesive, and is inserted through a hole in the PCB.

Abstract: Bond pad lift problems encountered during bonding are alleviated by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad. Conductive material fills the at least one opening, and electrically connects the top and bottom bond pads. In one embodiment, the at least one opening is a plurality of conductive vias. In another embodiment, the at least one opening is a ring-like opening extending around the peripheral region. In yet another embodiment, the at least one opening is one or more elongated slit-like openings.

Abstract: Damage to the package body and external leads of a leaded semiconductor device assembly is prevented by a carrier assembly. The carrier assembly includes a rigid bottom (lower) plate positively supporting the package body and providing a bottom cover for the external leads. A semi-rigid top (upper) plate positively holds the package body against the bottom plate, prevents movement of the package body with respect to the carrier assembly, and covers the external leads. Fasteners are provided for securing the upper plate to the lower plate, preferably at the four corners of the plates. In this manner, a durable "sandwich" structure is created, with the package disposed between the lower and upper plates and the body and leads well protected against damage.

Abstract: An automatic logic-model generation system operates on a schematic database and produces logic models incorporating accurate timing information. A verification process is also performed whereby the model is automatically verified for accuracy.