Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.

Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.

Abstract: An integrated infrared (IR) and full color complementary metal oxide semiconductor (CMOS) imager array is provided. The array is built upon a lightly doped p doped silicon (Si) substrate. Each pixel cell includes at least one visible light detection pixel and an IR pixel. Each visible light pixel includes a moderately p doped bowl with a bottom p doped layer and p doped sidewalls. An n doped layer is enclosed by the p doped bowl, and a moderately p doped surface region overlies the n doped layer. A transfer transistor has a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to a floating diffusion region. The IR pixel is the same, except that there is no bottom p doped layer. An optical wavelength filter overlies the visible light and IR pixels.

Abstract: An erbium (Er)-doped silicon (Si) nanocrystalline embedded silicon oxide (SiOx) waveguide and associated fabrication method are presented. The method provides a bottom layer, and forms an Er-doped Si nanocrystalline embedded SiOx film waveguide overlying the bottom layer, having a minimum optical attenuation at about 1540 nanometers (nm). Then, a top layer is formed overlying the Er-doped SiOx film. The Er-doped SiOx film is formed by depositing a silicon rich silicon oxide (SRSO) film using a high density plasma chemical vapor deposition (HDPCVD) process and annealing the SRSO film. After implanting Er+ ions, the Er-doped SiOx film is annealed again. The Er-doped Si nanocrystalline SiOx film includes has a first refractive index (n) in the range of 1.46 to 2.30. The top and bottom layers have a second refractive index, less than the first refractive index.

Abstract: A system and method are provided for controlling information flow from a channel service module (CSM) in an asymmetric channel environment. The method provides information for transmission to an OSI model PITY (physical) layer device with a channel buffer. The PHY device channel buffer current capacity is estimated. Information is sent to the channel buffer responsive to estimating the channel buffer capacity, prior to receiving a Polling Result message from the PHY device. Initially, Polling Request messages are sent to the PHY device, and Polling Result messages received from the PHY device, as is conventional. In response to analyzing the Polling messages, a transmission pattern is determined, which includes the amount of information to transmit and a period between transmissions.

Abstract: A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.

Abstract: An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

Abstract: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Abstract: A method is provided for fabricating a high quantum efficiency silicon (Si) nanoparticle embedded SiOXNY film for luminescence (electroluminescence—EL and photoluminescence—PL) applications. The method provides a bottom electrode, and deposits a Si nanoparticle embedded non-stoichiometric SiOXNY film, where (X+Y<2 and Y>0), overlying the bottom electrode. The Si nanoparticle embedded SiOXNY film is annealed. The annealed Si nanoparticle embedded SiOXNY film has an extinction coefficient (k) of less than about 0.001 as measured at 632 nanometers (nm), and a PL quantum efficiency (PLQE) of greater than 20%.

Abstract: A method is provided for forming an error diffusion-derived sub-resolutional grayscale reticle. The method forms at least one partial-light transmissive layer overlying a transparent substrate. At least one unit cell in formed in the transmissive layer. The unit cell is formed by selecting the number of reduced-transmission pixels in the unit cell, and forming a sub-pattern of reduced-transmission pixels in the unit cell. The unit cell is sub-resolutional at a first wavelength.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; data stream inputs below the first threshold and above the third threshold are a “0” if both the second and third bits are “1” values, and as a “1” if either of the second and third values is a “1”; data stream inputs above the second threshold and below the third threshold are a “1” if both the second and third bits are a “0” value, and as a “0” if either of the second and third values is a “0”.

Abstract: A sub-resolutional grayscale reticle and associated fabrication method have been presented. The method provides a transparent substrate, and forms a plurality of coincident partial-light transmissive layers overlying the transparent substrate. A pattern is formed, sub-resolutional at a first wavelength, in at least one of the transmissive layers. If there are n transmissive layers, the reticle transmits at least (n+1) intensities of light. In one aspect, each of the plurality of transmissive layers has the same extinction coefficient and the same thickness. In other aspects, the transmissive layers may have different thickness. Then, even if the extinction coefficients are the same, the attenuation of light through each layer is different. The transmission characteristics of the reticle can be further varied if the transmissive layers have different extinction coefficients. Likewise, the transmission characteristics through the sub-resolutional patterns can be varied.

Abstract: Reduced complexity inverse discrete cosine transform (IDCT) masks and a method for reducing the number of IDCT calculations in video decoding are provided. The method comprises: accepting an n×m matrix of DCT coefficients; performing (n?y) horizontal IDCT operations, where y is greater than 0; performing y scaling operations; and, generating an n×m block of pixel information. Some aspects of the method further comprise: performing (m?z) vertical IDCT operations, where z is in the range between 0 and m/2. In some aspects, performing (n?y) horizontal ICDT operations includes performing IDCT operations for the first (n?y) horizontal rows. Then, performing y scaling operations includes: selecting the DC component from the first position of each horizontal row; scaling the selected DC component; and, copying the scaled DC component into the remaining positions of each of horizontal row.

Abstract: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.

Abstract: A system and method are provided for transporting a serial stream via a lower speed network using multiple parallel paths. At a transmitter, an optical or electromagnetic waveform is accepted representing a serial stream of digital information, and unbundled into n virtual information streams. Each virtual information stream is divided into a sequence of segments. Each segment is encapsulated, creating a sequence of packets by adding a start indicator to the beginning of each segment, and a terminate indicator to the end of each segment. Each packet is disinterleaved across m lanes and reinterleaved into n branches of framed data. Optical or electromagnetic waveforms representing the framed data are transmitted via n network branches. A receiver is also provided, which essentially reverses the above-described transmission method.

Abstract: Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of conditional branch resolutions and predictions for a fetched conditional branch instruction. An associated instruction address is hashed with a left-shifted GHR value. The result is used to access a word in an indexed BHT stored in a single-port random access memory (RAM). The word comprises a branch direction count for the plurality of fetched conditional branch instructions. In a second clock cycle a conditional branch instruction is executed at an execute stage and the BHT is written with an updated branch direction count in response to a resolution of the executed conditional branch instruction.

Abstract: A system and method are provided for negotiating a link data rate in a communication system using a plurality of data rates. In a system including a first device network-connected to a second device, auto-negotiation (AN) messages are mutually transmitted. The AN messages indicate rate information such as preferred data rate capabilities, if the device has a dual-rate capability, or a single data rate capabilities. If the AN messages are mutually transmitted, a negotiated link data rate is established. However, if one of the devices cannot send AN messages, the other device times-out, and a link data rate is established at the data rate transmitted by the device that is not AN-capable.

Abstract: A system and method are provided for feed-forward equalization (FFE) in a transmission system. The method accepts a serial stream of input digital data signals. For each input data signal, a temporal sequence of signals is generated. Each of the signals in the temporal sequence is selectively shaped. Shaping map include varying the degree of amplification, modifying the slew rate, or varying the time delay. The contributions of the selectively shaped signals in the temporal sequence are then selectively weighted, and a summed output signal is transmitted.

Abstract: A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR.

Abstract: A system and method are provided for deinterleaving differential inverse multiplexed (DIM) virtual channels in a 40G Ethernet receiver. The method accepts a 10.3125 gigabits per second (Gbps) (10G) Ethernet virtual channel with 64B/86B blocks, including periodic Lane Alignment Marker (LAM) blocks. The 10G virtual channel is deinterleaved into two 5.15625 Gbps (5G) virtual channels by: 1) deinterleaving consecutive blocks from the 10G virtual channel into the 5G virtual channels in an alternating order, and 2) reversing the order of deinterleaving in response to each detected LAM block. Then, the method supplies the 5G virtual channels (i.e. to a MAC module).