Patents Represented by Attorney H. C. Lin
  • Patent number: 7605357
    Abstract: An array of photon counting phototoreceivers is constructed as an imager with micro-digitized pixels. Each photoreciever comprises a vertical cavity optical amplifier (VCSOA) as an optical amplifier, an avalanche photodiode as detector and an analog-to-digital converter (ADC) in an integrated structure. The ADC serves as a 1-bit digitizer and uses a resonant tunneling bipolar transistor RTBT. While the preferred embodiment of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made to the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of the present invention.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: October 20, 2009
    Assignee: Epitaxial Technologies
    Inventors: Ayub Mohammed Fathimulla, Olaleye Adetoro Aina, Harry Stephen Hier
  • Patent number: 7397133
    Abstract: A submount is used to mount a diode between two metal areas on the upper surface of a substrate. One of the areas is connected to a metal plate at the lower surface of the substrate through a via. The submount is clamped between two metal sheets. The top metal sheet has a through-hole for anchoring and self-aligning the diode. The electrodes of the diode are each coupled to one of the clamping metal sheets. Clamping metals provide pressure contact without soldering to the contact. But soldering can be alternatively used to enhance product reliability. Either the top metal sheet or the bottom metal sheet can be fully or selectively coating of solder for batch soldering at the contact point upon heating. The large metal plates and the large metal clamping sheets provide good heat sink and speedy soldering.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: July 8, 2008
    Inventor: Jiahn-Chang Wu
  • Patent number: 7381996
    Abstract: A LED chip is bonded on a large submount serving as a heat sink. The submount is punched out from a thin metal sheet together with two other sections of lead frames for the LED and held together with insulating material. The planar structure makes the package thin. A transparent lens may be mounted over the submount. More than one LED of same or different color can be mounted on the submount.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: June 3, 2008
    Inventor: Chen-Lun Hsin Chen
  • Patent number: 7339726
    Abstract: A vertical cavity semiconductor optical photoamplifer (VCSOA) is used as a modulating retro-reflector (MRR) as a pixel in an array. The boundary of the cavity in the VCSOA forms a mirror for reflecting an incident light as an amplified output.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 4, 2008
    Assignee: Epitaxial Technologies
    Inventors: Ayub Mohammed Fathimulla, Harry Stephen Hier, Olaleye A. Aina
  • Patent number: 7326303
    Abstract: This invention describes an apparatus, Scanning Localized Evaporation Methodology (SLEM) for the close proximity deposition of thin films with high feature definition, high deposition rates, and significantly improved material economy. An array of fixed thin film heating elements, each capable of being individually energized, is mounted on a transport mechanism inside a vacuum chamber. The evaporable material is deposited on a heating element. The SLEM system loads the surface of heating elements, made of foils, with evaporable material. The loaded thin film heating element is transported to the substrate site for re-evaporation. The re-evaporation onto a substrate, which is maintained at the desired temperature, takes place through a mask. The mask, having patterned openings dictated by the structural requirements of the fabrication, may be heated to prevent clogging of the openings. The translation of the substrate past the evaporation site permits replication of the pattern over its entire surface.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: February 5, 2008
    Assignee: Optoelectronics Systems Consulting Inc.
    Inventors: Fotios Papadimitrakopoulos, Thomas Samuel Phely-Bobin, Daniel Harrison Grantham, deceased, Faquir C Jain
  • Patent number: 7284896
    Abstract: A light emitting device with a top electrode and a bottom electrode is pushed by a plug to make contacts with either an upper metal plate or a lower metal plate each serving as one of the leads for an electrode of the light emitting devices. The plug is inserted through an opening larger than the light emitting device in the metal plate not in contact with the light emitting device but serving as another lead for the light emitting device. The plug is locked in place by means of threaded screw heads, snug-fit, snap-on buttons or an elastic sleeve. Thus, the light emitting device can be easily replaced without any wire bonding. A plurality of the light unit can be sandwiched between the upper metal plate and the lower metal plate.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: October 23, 2007
    Inventor: Jiahn-Chang Wu
  • Patent number: 7276723
    Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 2, 2007
    Assignee: Epitaxial Technologies
    Inventors: Ayub Mohammed Fathimulla, Harry Stephen Hier, Olaleye Adetord Aina
  • Patent number: 7276739
    Abstract: A light emitting diode (LED) includes a LED chip, which can transfer electrical power to electric-magnetic wave. A set of lead frame is enclosed by electrical isolator material to form a cavity. An optics lens seats on top of the cavity and is bonded to said electrical isolator material. A submount to carry said LED chip is soldered or adhered to the lead frame and forms the electrical contact from said LED chip to lead frame. A high transparency material is utilized to enclosed the LED chip.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 2, 2007
    Inventors: Chen-Lun Hsin Chen, Hsu-Keng Tseng, Jung-Hao Hung
  • Patent number: 7276741
    Abstract: The leads of a light emitting diode are made coaxial. The inner lead protrudes lower than the outer lead. The package is inserted into a spongy display panel for power supply. The display panel has three layers: a lower conducting layer for contacting said inner lead and a top conducting layer for contacting said outer layer, and an insulating layer between the top and the bottom layer. For LED with a bottom electrode and a top electrode, the LED can be mounted on the planar tops of the inner lead and the top electrode wire bonded to the outer lead, or the LED can be mounted on the side surface of the inner lead and the top electrode wire bonded to the outer lead. For LED with two bottom electrode, the LED electrodes can straddle over the planar tops of the inner lead and the outer lead, or the LED electrodes can straddle over the telescopic side surfaces of the two leads.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: October 2, 2007
    Inventor: Jiahn-Chang Wu
  • Patent number: 7245028
    Abstract: A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss which represents logical “0”, so that a default output is 1,0. When the split control pad is bonded with outside Vdd or Vss, both sections output “1,1” or “0,0” respectively. One of three possible logic word combinations can be selected to use for an IC.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: July 17, 2007
    Assignee: Lyontek Inc.
    Inventors: Chi-Cheng Hung, Ling-Yueh Chang
  • Patent number: 7234513
    Abstract: Heat from a heat generating device such as a CPU is dissipated by a heat sink device containing a recycled two-phase vaporizable coolant. The coolant recycles inside a closed metal chamber, which has an upper section and a lower section connected by a conveying conduit, and a wick evaporator placed in the lower section. The liquid coolant in the evaporator is vaporized by the heat from the heat generating device. The coolant vapor enters the upper section and condenses therein, with the liberated latent heat dissipated out through the inner top chamber wall. The condensed coolant is then collected and flows into the lower section, and further flows back to the wick evaporator by capillary action of the evaporator, thereby recycling the coolant. Space or a piece of element with parallel grooves is used to form at least one of the sections to reduce friction in the liquid flow path.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: June 26, 2007
    Assignee: National Tsing Hua University
    Inventor: Shwin-Chung Wong
  • Patent number: 7193303
    Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting forms a cantilever over said first metallic contact and the overhanging end of the cantilever is glued to said second metallic contact.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: March 20, 2007
    Inventor: Jiahn-Chang Wu
  • Patent number: 7194243
    Abstract: In a direct conversion receiver with zero-frequency intermediate frequency (IF) signal, the DC offset and 1/f noise of the IF signal is compensated by means of double-sampling. The first period of the doubling-sampling is a calibration phase, which stores the DC offset and the 1/f noise. The second period is a signal flow phase during which the stored DC offset and 1/f noise is connected in opposition with the IF signal to cancel the DC offset and 1/f noise.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: March 20, 2007
    Assignee: Maryland Semiconductor Inc.
    Inventors: Hung C. Lin, Weixin Kong
  • Patent number: 7190604
    Abstract: Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: March 13, 2007
    Assignee: Lyontek Inc.
    Inventors: Chi-Cheng Hung, Ling-Yueh Chang, Pwu-Yueh Chung
  • Patent number: 7166868
    Abstract: The electrodes of a light emitting diode (LED) is coupled to the terminals of a package with solderless pressure contacts. Each package is housed in a module with a bed on which the bottom electrode of the LED rests, and a pressure plate which is coupled to the top electrode of the LED. The pressure plate slides along four vertical posts to exert pressure to an LED package against a bed to form solderless pressure contacts. A plurality of LED packages can be lined up in a row to form a light strip, with the top pressure plate extended to form the bed of an adjacent module. A plurality of LED packages can also be arranged a matrix array display panel, where a plurality of lower terminals rests on one row of common bed of a number of parallel horizontal common beds, and where a plurality of upper terminals are pressed under a column of parallel vertical common pressure plates, so that any individual LED at the cross-point of a common bed and a common pressure can be randomly accessed.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: January 23, 2007
    Inventor: Jiahn-Chang Wu
  • Patent number: 7115168
    Abstract: Scanning localized evaporation and deposition of an evaporant on a substrate utilizes a mask assembly comprised of a series of mask elements with openings thereon and spaced apart in a stack. The openings are aligned so as to direct the evaporant therethrough onto the substrate. The mask elements are heated and the stack may include a movable shutter element to block openings in adjacent mask elements. The evaporant streams are usually vertical but some may be oblique to the substrate, and they may be of different materials.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: October 3, 2006
    Assignee: Optoelectronic Systems
    Inventors: Daniel Harrison Grantham, Thomas Samuel Phely-Bobin, Fotios Papadimitrakopoulos, Faquir C. Jain
  • Patent number: 7019898
    Abstract: A three-dimensional surface shape is produced from input numerical data. The shape of an elastic surface is determined by the positions of a first matrix of memory rods. The position of each of the memory rods is determined by a flexible sheet which is contoured by a second matrix of control rods and is computer-controlled. After control rods transfer the contour data to the memory rods, the control rods are reset to receive new contour data. Both the memory rod and control rod are fitted with two pneumatically controlled locking mechanisms, one for the X-coordinate and one for the Y-coordinate. When both locks on a particular rod are released the rod is free to move to a new position determined by an elevator. Once all of the rods have been adjusted, they are locked in position and the surface has been configured.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: March 28, 2006
    Inventor: Derrick John Page
  • Patent number: 7011146
    Abstract: Heat from a heat generating device such as CPU is dissipated by a heat sink device containing a recycled two-phase vaporizable coolant. The coolant recycles inside a closed metal chamber, which has an upper section and a lower section connected by a conveying conduit, and a wick evaporator placed in connection with the lower section. The liquid coolant in the evaporator is vaporized by the heat from the heat generating device. The coolant vapor enters the upper section and condenses therein, with the liberated latent heat dissipated out through the inner top chamber wall. The condensed coolant is then collected and flows into the lower section, and further flows back to the wick evaporator by capillary action of the evaporator, thereby recycling the coolant. Space or a piece of element with parallel grooves is used to at least one of the sections to reduce friction in the liquid flow path.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: March 14, 2006
    Assignee: NationalTsing Hua University
    Inventor: Shwin-Chung Wong
  • Patent number: 6998650
    Abstract: A clip is used to clamp a LED in place in a LED module. The clip has pliable conducting cover and can be latched to the upper lead metal of the LED module. The clip can be lifted for replacing a defective or color LED. A plurality of replaceable LEDs can be mounted a common metal substrate to form a display panel, and each LED can be clamped in position with clips straddling between parallel upper lead metal for electrical coupling to the top electrodes of the LED.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: February 14, 2006
    Inventor: Jiahn-Chang Wu
  • Patent number: 6992319
    Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3–10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: January 31, 2006
    Assignee: Epitaxial Technologies
    Inventors: Ayub M Fahimulla, Harry Stephen Hier, Olaleye A. Aina