Abstract: A projection exposure system, which is used to transfer a pattern from a reticle or mask onto a substrate, incorporates a projection optical system that is capable of maintaining the same performance as that which can be found in an ideal environment, even when the actual use environment (e.g. atmospheric pressure and temperature) is not ideal. In addition, the projection optical system is able to recover the same performance as in an ideal environment through relatively minor adjustment of its projection optical system even when atmospheric pressure significantly changes due to, e.g., a change in location and altitude where the system is used.

Abstract: A semiconductor device with a base region that terminates on the surface of a slot that surrounds the base region. The base region terminates substantially perpendicular to the surface of the slot. The collector-base junction has substantially no cylindrical or spherical curvature.

Abstract: A method of testing a semiconductor memory device using a parallel march pattern method of testing. All of the memory bits in a memory device are programmed to a first logic state. All of the memory bits in selected rows are programmed to a second logic state. All of the memory bits in rows adjacent to the rows programmed to the second logic state are read to determine if the memory bits programmed to the second logic state have caused the memory bits programmed to the first logic state in the adjacent rows to change logic state. The selected rows are determined by a periodicity value that can be values such as 4, 8, or 16. The periodicity determines the number of clock cycles needed to test the entire memory device. A periodicity of 8 requires only 8 clock cycles to test the entire memory device, regardless of the size of the memory device. The parallel march pattern method of testing can be by rows, by columns or by diagonals.

Abstract: A vehicle communications system having a remote control unit installed in the interior of a vehicle and a display unit located on the exterior of the vehicle. The display unit has an input from the remote control unit and an input from a vehicle interface module that has inputs from the vehicle such as the braking system and the turning signal system. The remote control unit is controllable by the driver in the vehicle and has a table of preset and preprogrammed messages selectable by the driver. The driver selects a message to be displayed and sends the message to the display unit. Any input to the vehicle interface module from the vehicle signaling systems overrides the signal input from the remote control unit unless the display unit is mounted on the front of the vehicle. The driver can select a message from a table of messages that are sequentially displayed on the remote control unit. The table of messages is stored on a flash memory in the remote unit and in a flash memory in the display unit.

Abstract: A microprocessor system integrated on a chip having one or more address generation devices, at least one memory location, and at least one peripheral unit. The address path is divided into two portions having a first logic unit conditioning the address from the one or more address generation devices on the first portion of the address path for gating onto the second portion of the address path. The first logic unit converts a single 16 bit address location into two 8 bit address locations. The first logic unit maintains a first address on the second address path when the CPU is in a next address pipeline mode. A second logic unit selects a memory architecture so that the system can address DRAM units having a various number of rows and/or columns.

Abstract: A method of manufacturing a semiconductor device to prevent uneven polysilicon gate dopant accumulation at the gate/gate oxide interface. A layer of gate oxide is formed on the surface of the silicon substrate, a layer of amorphous silicon is deposited on the gate oxide and a doped layer of amorphous silicon is deposited on the first layer. The first and second layers are deposited by chemical vapor deposition and an oxygen containing gas is selectively injected into the stream of silicon source gas depositing the first and second layers of amorphous silicon.

Abstract: A low cost objective lens system that provides complete axial color correction with no substantial residual color dependent aberrations such as spherochromatism or chromatic coma. The objective lens system includes a first lens element having an aspherical lens surface and a second lens element having a diffractive optical surface and an aperture disposed between the first and second lens elements. The axial separation of the aspherical lens surface and the diffractive optical surface may be determined by the condition 0.5<L.sub.A /efl<1.25 where L.sub.A is the axial distance from the lens element with the aspherical surface to the lens element with the diffractive optical surface and efl is the effective focal length of the objective lens system. The diffractive optical surface is optically dispersive and is preferably placed on the refractive lens element in the system having the highest optical power.

Abstract: Various embodiments of on chip-transformers constructed in separate metal layers in an insulator that serves as a dielectric which is formed on a substrate such as a silicon substrate. Windings with currents flowing in a first direction are constructed in a first metal layer and windings with currents flowing a second direction are constructed in a second metal layer. Windings in the first metal layer are connected to windings in the second metal layer by connectors such as vias. The transformer can be constructed in a balun layout, an autotransformer layout, a layout with the secondary separated from the primary, a layout with the secondary separated the primary and rotated with respect to an axis of the primary, a layout in which the transformer is a two stage transformer and with the first stage constructed orthogonal to the second stage, or a transformer in which the windings are constructed in a toroidal layout.

Abstract: A data structure to provide high performance in the transmit portion of an ethernet controller. The data structure includes the data to be transmitted, the STATUS information of the data to be transmitted, and the DESCRIPTOR information of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32 bit STATUS information is organized in four 8-bit bytes in a 32 bit row, and the 32 bit DESCRIPTOR information is organized in four 8-bit bytes in a 32 bit row. A one-bit tag field is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.

Abstract: In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature programmability rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. All cells in the memory device are subjected to a first sequence of programming pulses at a voltage lower than the standard programming voltage. The number of pulses in the first sequence of programming pulses is from 1-5. Those die that verify as having been successfully programmed are passed. Those die that do not verify as having been programmed are subjected to a second sequence of programming pulses at a voltage lower than the standard programming voltage. The number of pulses in the second sequence of programming pulses is from 10 to 15 pulses. Those that verify as being programmed are marked as good and those that do not are repaired and retested.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine predicted wafer electrical test measurements. The simulation tool combines in-line critical dimensions from previous from previous processes run on the current wafer lot, data from previous lots for processes subsequent to the process being run on the current lot and calibration simulation data obtained from the comparison of the predicted wafer electrical test measurements and collected wafer electrical test measurements taken from previous actual wafer electrical test measurements.

Abstract: A method of manufacturing an MOS transistor having a gate length dimension less than the dimension available by methods available with conventional manufacturing methods that are limited by optical diffraction in photolithography. The method includes forming a polysilicon gate structure on a gate oxide layer, forming a nitrogen-doped layer on the polysilicon gate structure, forming selected depth oxide sidewalls on the polysilicon gate structure and etching the nitrogen-doped layer and the oxide sidewalls.

Abstract: A method of determining classification codes for defects occurring in semiconductor manufacturing processes and for storing the information used to determine the classification codes. A wafer is selected from a production lot after the lot is sent through a first manufacturing process. The selected wafer is scanned to determine if there are defects on the wafer. Images of selected defects are examined and a numerical value is assigned to each of N elemental descriptor terms describing each defect. A classification code is determined for each defect based upon the numerical values assigned to the N elemental descriptor terms. The classification code and numerical values assigned to the N elemental descriptor terms are stored in a database. The wafer is sent through each sequential process and classification codes are assigned to additional defects selected after each sequential process.

Abstract: A microprocessor system having a first read path from memory and a second read path from peripheral units and an isolation buffer to isolate the first read path from the second read path. The system also has a first write path to memory and a second write path to peripheral units and an isolation buffer to isolate the first write path from the second write path. The isolation buffers also isolate the write paths from the read paths. Also included is a monitoring path between the peripherals and an external bus to allow program monitoring of data in the peripheral units.

Abstract: A semiconductor device having the base and collector surrounded by a continuous tungsten filled slot as ground plane. The portion of the tungsten filled slot over the buried layer extends beyond the surface of the buried layer and the portion of the tungsten filled slot not over the buried layer extends beyond the interface between the epitaxial layer and the substrate.

Abstract: Projection lens systems, which are used to transfer a pattern from a reticle onto a substrate, incorporate projection optical systems that are capable of maintaining the same, or increased performance, as the current projections lens systems, achieve excellent aberration correction, and which have high numerical apertures.

Abstract: A method of manufacturing an SRAM cell with polysilicon diode loads using standard logic technology processing. A P+ polysilicon area and an N+ polysilicon are forms a lateral PN junction. In standard logic technology processing the lateral PN junction is shorted out. In the present invention the lateral PN junction is allowed to function as a polysilicon diode load and an ancilliary lateral PN junction is shorted using a polycide cap layer.

Abstract: A projection exposure system, which is used to transfer a pattern from a reticle or mask onto a substrate, incorporates a projection optical system that is capable of maintaining the same performance as that which can be found in an ideal environment, even when the actual use environment (e.g. atmospheric pressure and temperature) is not ideal. In addition, the projection optical system is able to recover the same performance as in an ideal environment through relatively minor adjustment of its projection optical system even when atmospheric pressure significantly changes due to, e.g., a change in location and altitude where the system is used.

Abstract: A method for navigating directly to defects on a blank wafer caused by particles dropped from process tools. A blank wafer is marked with fiducial marks, the number of initial defects on the blank wafer is determined and the position coordinates of the initial defects and the fiducial marks are recorded. The blank wafer is placed into a selected process tool and the additional defects that are caused by particles dropped from the process tool are detected in an inspection tool and their position coordinates are determined and recorded as well as the position coordinates of the fiducial marks. The blank wafer is then placed in an analysis tool that is able to navigate directly to each of the additional defects at a high magnification using the position coordinates of the fiducial marks.

Abstract: A method of manufacturing a raised source/drain MOSFET by depositing amorphous silicon on the partially formed MOSFET having the gate and gate oxide spacers formed, ion implanting to form the appropriate source/drain junctions, annealing wherein epitaxial growth takes place in regions where the amorphous silicon is over silicon, and etching the remaining amorphous silicon. A layer of refractory metal is deposited and a second anneal converts the refractory metal overlaying silicon to silicide.