Abstract: A semiconductor device having the base region surrounded by at least two continuous slots. The collector region is surrounded by at least one continuous slot formed as a continuation of one of the at least two continuous slots surrounding the base region. The portions of the slots that are over the buried layer extends beyond the surface of the buried layer and the portions of the slots not over the buried layer extends beyond the interface between the epitaxial layer and the substrate. The slots are filled with either polysilicon or tungsten. The base region terminates on the surface of the innermost slot surrounding the base region. The boundary of the base region terminates substantially perpendicular to the surface of the surrounding slot.

Abstract: A method to accurately classify defects on a semiconductor wafer wherein a scanning tool detects defects and assigns values to parameters that are characteristic of each defect. The values of the characteristic parameters represent a thumbprint of each defect and the defects are placed into "bins" according to the thumbprint of each defect. A sample of defects in each bin is analyzed and assigned a classification code.

Abstract: A method of manufacturing a semiconductor device with a steep retrograde profile. The threshold voltage adjust dopant layer and the punchthrough prevent dopant layer are formed in the substrate. All surface capping layers are removed from the active device regions and, the semiconductor device is placed in a chamber and a high vacuum is established after which an inert atmosphere is introduced into the chamber. The anneal to repair the damage to the lattice and to activate the dopant ions in the dopant layers is done in the inert atmosphere with the surface of the substrate maintained clean, that is, free from a capping oxide or other layer formed on the surface of the substrate.

Abstract: A projection lens system that is used to transfer a pattern from a reticle onto a wafer, incorporates a projection optical system that is capable of maintaining the same, or increased performance, as the current projection lens systems, and that achieves excellent aberration correction, has a numerical aperture of at least 0.6, an exposure field area of at least 18.7.times.18.7 mm or at least 26.45 mm diameter at the wafer plane, and has a total lens thickness to length ratio less than 0.64 and uses 5 or less aspherical lens surfaces.

Abstract: A method of assembling a substrate and die in a flip chip configuration uses a non-hazardous cleaning solvent to clean the flux residue. The non-hazardous cleaning solvent utilized is Ionox obtained from Kyzen Corporation. Optimized process parameters are: time 10-30 minutes, temperature 70-90.degree. C., pressure 40-70 psi, rotation speed and reversals 100-1000 rpm and 24-100 reversal cycles.

Abstract: Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.

Abstract: Projection lens systems for transferring a pattern on a reticle onto a wafer having an aplanatic lens element. The aplanatic lens element has a shape factor between 0.1 and 0.224, the projection lens system satisfies the condition:-2.0<f.sub.ap /F<-0.6251, where f.sub.ap is the focal length of the aplanatic lens element and F is the focal length of the projection optical lens system. The projection optical lens system further satisfies the condition 2.6<.vertline.f.sub.G3 /f.sub.G .vertline.<4.64.

Abstract: A package providing low stress mounting for semiconductor die having a base plate, a flexible printed wiring circuit wrapped around the base plate with a first portion of the flexible printed wiring circuit adhesively attached to an external side of the base plate and a cap attached to the periphery of the base plate forming a space between the base plate and the cap in which a second portion of the flexible printed wiring circuit is disposed. The space formed between the base plate and the cap is filled with air, a soft gel, or a material such as RTV. The semiconductor die are mounted on the portion of the flexible printed wiring circuit disposed in the space formed between the base plate and the cap. The portion of the flexible printed wiring circuit adhesively attached to the base plate has pads that communicate to an external device. The pads are in electrical communication with the semiconductor mounted on the flexible printed wiring circuit.

Abstract: An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.

Abstract: A method of obtaining accurate actual ion implantation equipment used in ion implantation processes during the manufacture of semiconductor devices. A monitor structure for each ion implant process is implanted with ions during the ion implant process. A control monitor structure is implanted with boron ions. The concentration profiles of all implanted monitor structure are determined during wafer electrical tests (WET). The as-implanted concentration profile is determined for the boron-implanted control monitor structure and the thermal budget of the manufacturing process is determined. The as-implanted concentration profiles of the remaining monitor structures are determined using the thermal budget determined from the boron-implanted control monitor structure. The actual operating parameters of the ion implantation equipment is determined from the as-implanted concentration profiles.

Abstract: A method of precisely measuring electrical parameters in integrated circuits in a face down semiconductor device in which a portion of the semiconductor substrate is removed from the semiconductor device and an SEM microprobe is directed onto selected regions of the surface exposed by the removal of the semiconductor substrate. The microprobe is directed to selected regions of the exposed surface by a computer generated mapping system. One of the selected regions that the microprobe is directed to is a region of the exposed surface overlying a depletion region associated with a drain of a transistor in the semiconductor device. The voltage variation on the exposed surface caused by the expansion and shrinking of the depletion region is measured by the microprobe. Another region that the microprobe is directed to is a region of the exposed surface overlying an insulator and the microprobe detects the voltage of a conducting electrode under the insulator is measured via capacitive coupling.

Abstract: An apparatus and method for transferring a pattern on a reticle onto a wafer includes a projection lens system having four groups of lens elements. The projection lens system satisfies the conditions: 0.3<.vertline.f.sub.G2 /L.vertline.<4.46, 1.8<.vertline.f.sub.G3 /L.vertline.<4.8, 0.05<.vertline.f.sub.G2 /f.sub.G3 .vertline.<0.25, 0.77<.vertline.f.sub.G1 /f.sub.G4 .vertline.<1.1, 0.17<f.sub.G4 /F<0.195, 0.14<f.sub.G1 /F<0.191, and having a numerical aperture equal to or greater than 0.60.

Abstract: A semiconductor device and a method of making the semiconductor device, the semiconductor device having a base region wherein the base region is surrounded by a slot. The sideways depletion region of the collector-base junction terminates on the slot thus reducing the sideways spreading of the collector-base depletion region.

Abstract: A timer counter with multiple timers in a pipelined architecture in which the multiple timers are serviced in the pipeline. The timer counter includes a control unit having a first control section and a second control section for sequencing the servicing of each of the multiple timers in a pipeline. The first and second control sections provide a pipeline sequence of the total required service of the timer counter. The pipeline architecture allows the multiple timers to be serviced in a pipeline without increasing the overall number of clocks.

Abstract: A method of determining classification codes for defects occurring in semiconductor manufacturing processes and for storing the information used to determine the classification codes. A wafer is selected from a production lot after the lot is sent through a first manufacturing process. The selected wafer is scanned to determine if there are defects on the wafer. Images of selected defects are examined and a numerical value is assigned to each of N elemental descriptor terms describing each defect. A classification code is determined for each defect based upon the numerical values assigned to the N elemental descriptor terms. The classification code and numerical values assigned to the N elemental descriptor terms are stored in a database. The wafer is sent through each sequential process and classification codes are assigned to additional defects selected after each sequential process.

Abstract: A defect management system with a method to identify and reclassify previously classified propagator defects. The defect management system also has a method of identifying cluster defects and selecting at least one cluster defect to classify.

Abstract: Lens systems for wide band infrared camera having a bandwidth of 1-5 .mu.m with a low f-number and 100% cold stop efficiency.

Abstract: A semiconductor device formed in a semiconductor substrate with a low hydrogen content barrier layer formed over the semiconductor device. The barrier layer is implanted with phosphorus ions. The semiconductor device may have a hydrogen getter layer formed under the barrier layer. The barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between 1000 and 2000 Angstroms and is a PSG, BPSG, PTEOS deposited oxide film, or BPTEOS deposited oxide film. Interconnects are made by a tungsten damascene process.

Abstract: A method of manufacturing a semiconductor device to negate the effects on the device performance caused by defects on the silicon substrate. An oxygen doped amorphous silicon layer is deposited onto the gate region of the semiconductor device and can have a thickness of less than 5 nanometers. The amorphous silicon provides a conformal layer over the defects on the silicon substrate. The oxygen doping of the amorphous silicon maintains the conformality of the amorphous silicon layer during subsequent processing by preventing the formation of large amorphous silicon grains during a crystallization process. The resulting silicon oxide layer has increased uniformity and can have a thickness of less than 10 nanometers.

Abstract: Submicron nLDD CMOS logic devices with improved current drive and reduced reverse short-channel effects having heavily doped As and lightly doped P nLDD region.