Abstract: A masking method for use in a silicide formation process is disclosed herein which prevents an oxide etching solution from tunneling under a photoresist masking layer and damaging oxide spacers not intended to be etched. This process may be used during the formation of a bipolar or MOS transistor formed in an isolated silicon island. A mask opening used to etch exposed oxide spacer portions is made to not expose any parasitic oxide spacers formed along an edge of the isolated silicon island. In this way, an oxide etch solution is prevented from tunneling along the parasitic oxide spacer and reaching any intersecting oxide spacers not intended to be etched. The desired oxide spacers will thus be intact to properly isolate silicide portions formed over exposed silicon and polysilicon surfaces.

Abstract: A tristate driver interfaces a 3.3 volt digital circuit to a bus that supports both 3.3 and 5.0 volt digital signals. In one embodiment, the pullup circuit path includes a P-channel MOSFET which is backgated by a backgate voltage generator and gated by a gate voltage generator that receives its drive voltage from a comparator and is controlled by an enable circuit. The pulldown circuit path includes an N-channel MOSFET which is controlled by the enable circuit. Current leakage through the pullup circuit is minimized when overvoltage occurs on the bus by suitably gating and backgating the pullup MOSFET. In another embodiment, two MOSFETs are used in the pullup circuit. Both are backgated by a backgate voltage generator, while one is gated by a gate voltage generator that receives its drive voltage from the bus while the other is controlled by an enable circuit. The pulldown circuit path includes an N-channel MOSFET which is controlled by the enable circuit.

Abstract: Two dimensional data structures are represented by quadtree codes with embedded Walsh transform coefficients. The quadtree code permits both variable block size inherent in quadtrees, and the calculational simplicity of Walsh transform descriptions of nearly uniform blocks of data. Construction of the quadtree is calculationally simple for implementation in a digital system which does a bottom-up determination of the quadtree because Walsh transform coefficients and a measure of the distortion can be recursively calculated using only Walsh transform coefficients from the previous level in the quadtree. Uniform step size quantization, which is optimal for variable length coding and generalized gaussian distributions, permits fast encoding and decoding of quadtree code.

Abstract: A digital clock divider is capable of dividing a clock frequency n by N.5, where N is an integer, and includes a closed loop of flip-flops numbering twice N.5, and an additional flip-flop to which the clock signal is applied through an inverter, the output signal of the additional flip-flop is 180.degree. out of phase with a signal from a flip-flop of the closed loop. The 180.degree. out-of-phase signals are applied to an OR2 gate, the output signal of which has a frequency of n (clock signal) divided by N.5.

Abstract: A complementary transistor class AB output stage (200) utilizes a complementary pair of output drivers (220, 222) connected in series between the power supply rails (210, 216) to furnish the stage output. An output driver (206) is a composite pair of transistors in a Darlington configuration, which boosts the current gain and input resistance of the output stage. Bases of the output drivers are connected by a complementary pair of parallel connected drivers (226, 228), which function as common base level shifters. Quiescent bias of the output drivers is achieved by a pair of constant current transistors (232, 238) that are operated as complementary current mirrors. Inputs to the mirrors are relatively low current sink (252) and source (250) supplies.

Abstract: To exchange data in the same position in the hybrid ring control cycles in two FDDI-II rings, the cycles of the different rings are phase and frequency aligned. To achieve phase alignment, a hybrid multiplexer in one of the rings monitors the cycles on the other ring and starts a cycle when the hybrid multiplexer detects a starting delimiter on the other ring. In order to achieve frequency alignment, 8 KHz references produced by two hybrid multiplexers on the two respective rings are provided to a circuit that selects one of the references to determine the frequency for synchronizing cycle outputs of both hybrid multiplexers.

Abstract: A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K.

Abstract: A test circuit (200) furnishes a low battery level signal on the basis of a comparison between a first ratio of the battery potential when the battery (206) is unloaded and a second ratio of the loaded battery potential. The battery test circuit includes a potential divider (210), a comparator (250) and a potential sampler including a storage element (240), a controller (260), a control line (266) and a switch (268). The potential divider is coupled to the battery and includes a first tap (226) and a second tap (224). The potential sampler, which includes a storage element (240), is coupled to the first tap through a switch (268) so that a first ratiometric portion of the unloaded battery voltage is stored on the storage element. The comparator has a first input that is coupled to the storage element and a second input that is coupled to the second tap.

Abstract: A multiple-gap head for transferring data to or from a storage medium is disclosed. Data read by the gaps are directed over a plurality of serial data paths where the data are processed and synchronized. In some embodiments, all or part of a data synchronizer is shared by the serial data paths. The data are then assembled into a parallel data stream for delivery to a computer. Reading the data simultaneously with multiple gaps increases by several times the rate at which data can be transferred to or from a storage medium. In accordance with another aspect of the invention, a three-gap head is provided to reduce or eliminate the cross-talk or noise fringe problems which reduce the track density in a storage medium. A signal attenuator and a signal inverter are connected to each of the side gaps and the outputs thereof are summed with the signal originating at the center gap, such that the inverted signals from the side gaps cancel any cross-talk originating at the center gap.

Abstract: A differential mode voltage controlled oscillator (VCO) includes an odd number of delay cells. Each delay cell has a pair of input terminals and a pair of output terminals with the input terminals of each delay cell being connected to the output terminals of a preceding delay cell in a ring. Each delay cell has a delay time for inverting a complementary pair of signals from which a clock signal is derived. A positive temperature coefficient voltage-to-current converter receives the control voltage of the VCO and controls the maximum currents (and therefore the delays) of the delay cells. A pair of cross-coupling transistors in each delay cell keeps the signals on the output terminals out of phase (complementary). The cross-coupling transistors have sizes which maximize gain of the delay cells at the threshold voltages of the cross-couple transistor and thereby increase output voltage swing at high frequencies.

Abstract: In a BiCMOS process, a gate oxide is grown over the MOS transistors and over the base regions of the bipolar transistors. The base is implanted through the gate oxide and, in some embodiments, through a thin polysilicon layer overlying the base oxide. Then an opening is etched over the base regions in the thin polysilicon layer and the gate oxide, another polysilicon layer is deposited, and the two polysilicon layers are patterned to provide emitter contact regions and gate regions. The polysilicon etch terminates on the gate oxide. After an LDD implant or implants, an insulating layer is deposited and etched anisotropically to create spacers on the sidewalls of the emitter contact regions and the gate regions. During the etch, the gate oxide is etched away around the spacers to expose the extrinsic base regions and the source and drain regions.

Abstract: An op-amp incorporates an input stage composed of two complementary long-tailed transistor pairs driven in parallel from the input terminals. A bias supply circuit provides the tail currents which are proportioned so that the total tail current adds up to a constant sum. The bias circuit proportions the tail currents, relative to the common mode voltage, so that at least one long tailed pair will function even when the common mode is driven to the supply rail potential. The bias supply current includes cascode connected transistors to provide the tail currents and the input circuit includes active clamping transistors.

Abstract: An integrated circuit voltage regulator employs a PNP pass transistor to produce a low dropout voltage. Saturation in the pass transistor produces excessive substrate current which appears in the form of wasted current which lowers the regulator efficiency. A current conducted by the sat catcher circuit is employed to avoid pass transistor saturation. The sat catcher is controlled dynamically so the dropout voltage is minimized and the voltage regulator maintains good performance at high regulator output currents.

Abstract: A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

Abstract: A high speed operational amplifier includes a differential amplifier input stage capable of producing a pair of complementary differential outputs. Complementary current mirrors receive the differential signals out of the first stage and combine them at a common output node for amplification by an output buffer. The circuit can be operated at low power and produces a high slew rate.

Abstract: A process for forming field effect transistors having self-aligned source/drain contact includes: forming an gate overlying a portion of a semiconductor; forming a first sidewall spacer on the gate; forming a source/drain region in the semiconductor; depositing a conductive layer over the semiconductor so that a step is formed in the conductive layer in a region overlying the gate and the first sidewall spacer; forming a second sidewall spacer on the step; forming a protective layer over a portion of the conducting layer not covered by the second sidewall spacer; removing the second sidewall spacer to expose a portion of the conductive layer but leave covered a portion of the conductive layer underlying the protective layer; and removing the exposed portion of the conductive layer to leave a portion of the conductive layer in contact with the source/drain region and electrically isolated from the gate. The portion of the conductive layer left is the self-aligned contact.

Abstract: A P-channel floating-gate MOS transistor is used to detect and measure positive mobile ions in the oxide layers of a semiconductor device. The transistor is first "programmed" by applying a voltage close to the breakdown voltage of the transistor, which causes electrons to tunnel through the oxide underlying the floating gate and to become trapped on the floating gate. This results in a negative voltage on the floating gate, which turns the transistor on and causes a first current, I.sub.DS0 to flow through the transistor. The semiconductor device is then baked, or heated, to accelerate the movement of positive mobile ions attracted to the negative charge previously trapped on the floating gate. Any positive mobile ions collected by the floating gate will neutralize a portion of the negative charge on the floating gate and will create a less negative voltage on the floating gate, resulting in a lesser current through the device after the bake.

Abstract: In a bipolar transistor, the collector and the base are formed in an isolation region laterally bounded by a field insulator. The isolation region corners are spaced far from the emitter to reduce the collector-emitter leakage current. The base does not extend laterally throughout the isolation region. Thus the base is small and the collector-base capacitance is small as a result. Those corners of the isolation region that are not covered by a base contact region are covered and contacted by an insulator. This insulator prevents the field insulator from being pulled back during wafer clean steps. Consequently, the field insulator does not expose the collector. Further, the insulator covering the corners prevents the metal silicide on the surface of the extrinsic base from contacting the corners. The insulator overlying the corners thus reduces the collector-base leakage current.

Abstract: A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.