Abstract: A method of manufacturing semiconductor devices wherein a partially completed semiconductor device having a first and second layer of interlayer dielectric and a first and second etch stop layer has the second etch stop layer masked and etched with an etch pattern having dimensions of the trench structure to be formed in the second interlayer dielectric. The second layer dielectric and first etch stop layer are then masked and etched with an etch pattern having dimensions of the via structure to be formed in the first interlayer dielectric. The remaining portions of the photoresist is removed and exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric are then etched simultaneously. The via structure and trench structure are then simultaneously filled with a conductive material.

Abstract: A method of assembling a substrate and die in a flip chip configuration using a no clean flux. The no clean fluxes have sufficient chemical activity to activate solder bumps contacting bond pads to form reliable solder joints, sufficient tackiness to hold the substrate and die in alignment with the solder bumps contacting the bond pads, and a viscosity to enable a high volume manufacturing process to be used. The no clean fluxes leave a minimal amount of residue during a reflow process that does not interfere with an underfill operation and does not adversely affect the solder joints. The no clean fluxes that can be used for this application are RM1919 from Alpha Metals, Co. and H208 from Indium Company.

Abstract: An automated method of applying flux to substrate on which a semiconductor chip is to be assembled in a flip chip configuration by applying a controlled amount of flux to the substrate by a brush that applies the flux to the substrate in a programmed pattern of strokes thereby overcoming the surface tension of the flux/substrate surface. The programmed pattern of brush strokes is determined empirically for the specific combination of substrate and chip that is being assembled and is thus repeatable and operator independent. The empirically determined program also determines the amount of flux that will be applied to the substrate for the specific combination of substrate and chip being assembled. The empirically determined program is applied to a mechanical stage that moves the brush and to a flux reservoir by a CPU.

Abstract: A multiple chip hybrid package using bump technology having multiple chips electrically connected using a flip chip technology such as solder bump technology. Portion of at least one chip is electrically connected to electrical leads connecting terminals inside the package to pins outside the package.

Abstract: A method of utilizing associated process data parameters in the manufacture of semiconductor wafers by converting tool-based data to lot based data in order to predict wafer electrical test results from measured in-line critical dimensions, lot based data and the converted tool-based data. The converted tool-based data is obtained by interpolating data between a measurement obtained from a tool at a first time and a measurement obtained from the tool at a second time. The data association is obtained using LaPlace-Everett interpolation. The converted tool-based data can also be obtained by extrapolating data from the historical measurements taken from the tool.

Abstract: A method of manufacturing a semiconductor device with improved adhesion between the local interconnect etch stop layer and the thermal oxide in an isolation region. The thermal oxide is treated with an NH.sub.3 /N.sub.2 plasma. The local interconnect etch stop layer is either silicon nitride or silicon oxynitride. A layer of a dielectric material such as PECVD SiO.sub.2 is formed on the local interconnect etch stop layer.

Abstract: A method of filling trenches in a semiconductor wafer with a conductive material is disclosed by selectively electroplating the semiconductor wafer. The trenches are lined with a barrier layer and a seed layer and the semiconductor wafer is submerged in a solution having ions of the selected conductive material. An electrical potential is applied to the electroplating solution and the semiconductor wafer. The seed layer in the trench causes the conductive material ions to be plated in the trench.

Abstract: A method for the precise removal of the backside silicon on face down semiconductor devices to obtain a planar surface to allow electron beam microprobe analysis of the semiconductor device. The backside silicon is removed by plasma etching in a fluorocarbon based chemical plasma. The epitaxial layer in a CMOS device acts as an etch stop and the buried oxide layer in an SOI device acts as an etch stop.

Abstract: A multichip integrated semiconductor device having a portion of a first chip bonded to electrical leads in a package using a flip chip technology such as solder bump technology and a second chip bonded to a second portion of the first chip using a flip chip technology such as solder bump technology.

Abstract: A method of manufacturing a semiconductor device with increasing threshold voltage for parasitic transistor by forming a low power-low pressure phosphosilicate glass layer on the active regions and the field oxide regions.

Abstract: A method of using universal alignment marks on a semiconductor wafer that allows the accurate alignment of scanning and analysis tools in relation to the semiconductor wafer. The information in the universal alignment marks are utilized by a vendor generated algorithm incorporated into the respective scanning or analysis tools to accurately position the tool in relation to the semiconductor wafer.

Abstract: A method of manufacturing a semiconductor wafer in a chamber having a chuck and in which temperature changes in the chamber cause residual manufacturing materials to fall onto the surface of a production wafer placed on the chuck. When the temperature of the chamber is to be changed, a protection wafer is placed on the surface of the chuck. When the temperature has been changed, the protection wafer is removed from the surface of the chuck and a production wafer is placed on the surface of the chuck and clamped. When the process is complete the production wafer is removed and the protection wafer is placed on the chuck.

Abstract: A semiconductor device with first and second types of devices formed in a semiconductor substrate with a barrier layer formed over the surface of the semiconductor device including over the first and second types of devices with the barrier layer removed from over the first type of device. The first type of device is a positive charge sensitive device such as a nonvolatile memory device. The semiconductor device has a hydrogen getter layer formed under the barrier layer.

Abstract: A method of erasing a flash memory cell to suppress bi-directional tunnel oxide stress that includes applying a negative voltage to the control gate of the flash memory cell, applying a bias voltage to the substrate of the flash memory cell and applying a bias voltage to the drain of the flash memory cell that equals the bias voltage applied to the substrate minus a fraction of a diode voltage drop across the drain junction formed between the drain and the substrate. The bias voltage applied to the drain is selected so that the drain junction is not forward biased. The fraction is in the range of 20% to 80% of the diode voltage drop.

Abstract: A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test measurements that are compared to a set of target wafer electrical test measurements to obtain a set of optimized process parameters for the equipment for the next process. The optimized process parameters are compared to the equipment characteristics for the equipment of the next process and the process parameters for the next process are automatically adjusted.

Abstract: A defect management system with a method to update a database with defect data concerning propagator defect data. Defect data obtained from each layer formed on a semiconductor wafer is stored in a relational database. Defect data determined in a current layer to be defect data for a defect observed in a previous layer is defined as data concerning a propagator defect. Propagator defect data is used to update the data in the database relating to the previous layer.

Abstract: A method of manufacturing a semiconductor device including a step of filling crevices or non-level regions formed during the manufacture of the semiconductor device with a spin-on dielectric material. The spin-on dielectric material prevents conductive material from filling the crevices and causing the device to fail.

Abstract: A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench.

Abstract: An anamorphic system and method having first and second reflective anamorphic surfaces producing different magnifications in orthogonal directions in a collimated beam of radiation incident on the first anamorphic surface. The anamorphic surfaces have parabolic cross-sections in the two orthogonal directions. The parabolic cross-sections have base radii of curvatures and the magnifications in the first and second directions are determined by the ratio of the base radii of curvatures in the first and second directions.