Abstract: A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate. In a second embodiment, the source and drain regions are formed without a photoresist layer by ion implantation and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate.

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending requests from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

Abstract: A method to monitor boron penetration and optimize process parameters in the fabrication of a semiconductor device have an n.sup.+ or a p.sup.- -polysilicon gate. The charge-to-breakdown Q.sub.BD value is used to monitor the boron penetration into the polysilicon/gate oxide interface. Values of Q.sub.BD for various values of process parameters are determined and optimized values for these process parameters are derived.

Abstract: A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.

Abstract: An x86 microprocessor system with a process identification system which stores a number assigned to each process run by the microprocessor system and associates this number with instructions, data, and information fetched and stored in a cache or translation lookaside buffer (TLB) during the execution of the process. Upon a process or context switch, the instructions, data, and information are not automatically flushed from the cache and TLB. The instructions, data, and information are replaced only when instructions, data, and information for a new process require the same cache memory locations or the same TLB memory location. The cache and TLB may include a valid bit block and a tag block that includes memory locations for storing the pertinent process identification number for each entry.

Abstract: Interconnect via structures in a semiconductor integrated circuit having low resistance. The interconnect via structures connect metal layer structures in the semiconductor device and extend down at least one side of the metal layer structures. The interconnect via structures can extend down a second side of the metal layer structures and can extend down the end of the metal layer structures. The interconnect via structures extend beyond the sides and the end of the metal layer structures by a distance u where u is 1/4 to 1/2 F, where F is a feature of the design rule being used to manufacture the semiconductor device.

Abstract: A method of manufacturing a polysilicon plug in an integrated circuit semiconductor device wherein the polysilicon plug is selectively doped to act as a resistive load or alternatively to act as a diode load. The polysilicon load can be used in an SRAM memory cell.

Abstract: A large aperture wide angle zoom lens system including four groups of lenses. The four lens groups, viewed from the object side, include a first group with negative refractive power, a second group with positive refractive power, a third group with negative refractive power, and a fourth group with positive refractive power. The zoom lens system is capable of maintaining the position of the image constant during zooming, has fine imaging performance despite a large zoom ratio of 2.times. and a speed which is as fast as F/2.8 with an angle of view of 84.degree. on the wide side.

Abstract: A method of manufacturing a semiconductor device with reduced hot-carrier induced degradation wherein a nitrogen species is introduced into the gate oxide layer. The introduction of the nitrogen species may be done after the gate etch, after the spacer material deposition, or after the spacer etch. The nitrogen species may also be introduced into the gate oxide after both the gate etch and the spacer material deposition or after both the gate etch and the spacer etch or after all three steps.

Abstract: An automated wafer defect management system in which wafer defect data are collected from wafer inspection instruments, converted into a standard data format and made available through a central database system to workstations for review, analysis, and evaluation.

Abstract: Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels.

Abstract: In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature erase rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. Selected cells of the memory device are subjected to a first sequence of erasure pulses at a high voltage until the selected cells are verified erased or until a first maximum number of erasure pulses has been reached, recording the number of pulses required to erase the selected cells, reading and repairing any defective memory cells, and subjecting all cells to a second sequence of erasure pulses until all cells are verified erased or until a maximum number of pulses has been reached wherein the second maximum number is a multiple of the recorded number.

Abstract: A method of testing Flash memory devices by performing wafer sort testing on main array cells and redundancy array cells of the Flash memory device and performing class testing on redundancy array cells only. There is a major savings of testing time with no decrease in quality of the final product.

Abstract: An accurate method of measuring the two-dimensional doping profile of a semiconductor by measuring an electrical parameter along a path of a dopant iso-concentration. Thin vertical or horizontal slices of the semiconductor integrated circuit are provided and are probed to allow the electrical parameter to be measured through a single concentration area.

Abstract: A method of accurately determining the composition of a dielectric film in a semiconductor device by performing a compositional analysis on a film only portion of the semiconductor device.

Abstract: A data transceiver includes a transmitter connected at one end of a data transmission line and a receiver connected at the other end of the data transmission line. At least some portions of the transceiver are formed in CMOS. A temperature compensation circuit is connected to selected components of the transceiver to correct for temperature-induced variations in currents through those components. The temperature compensation circuit includes a pair of transistors connected, respectively, in parallel conduction paths. The respective width-to-length ratios of the channels of the transistors are unequal, and their gates are tied together. The current through the larger transistor varies directly with temperature, and this current is reflected in a current mirror transistor that is connected to the shorted gates of the transistor pair.

Abstract: A video image frame consisting of a two-dimensional array of picture elements (pixels) is decomposed into a set of rectangular image portions (tiles). Within each tile, variance between pixel intensity values is less than a predetermined value. A tile is encoded by a value set identifying the tile and including a single intensity value for all pixels in the tile. Frame-to-frame variation of the video image is encoded by inter-frame tile comparison and encoding of sub-tiles representative of change from a previous frame to a current frame.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed.