Abstract: An improved dual metallization process in which self-aligned tungsten contacts are formed to closely-spaced emitter or source sites in RF power silicon devices. Low-resistivity ohmic contacts are made by selectively depositing tungsten on the exposed silicon surfaces as a first metal layer without a photomasking process and after a dielectric layer deposition and via opening process. The metallization process is completed by depositing a second metal or polysilicon layer on the dielectric layer and through vias to selected tungsten contacts. The tungsten combines with doped silicon in the emitter or source regions to form the low-resistivity ohmic contacts without the requirement of a platinum or palladium deposition and siliciding step as in prior art. The tungsten is preferably chemical-vapor-deposited in a two-temperature step when a first few hundred Angstroms of tungsten are grown at a low temperature on the order of 250.degree. C.-350.degree. C.

Abstract: The invention described herein relates generally to the field of signal processing for signal reception and parameter estimation. The invention has many applications such as frequency estimation and filtering, and array data processing, etc. For convenience, only applications of this invention to sensor array processing are described herein. The array processing problem addressed is that of signal parameter and waveform estimation utilizing data collected by an array of sensors. Unique to this invention is that the sensor array geometry and individual sensor characteristics need not be known. Also, the invention provides substantial advantages in computations and storage over prior methods. However, the sensors must occur in pairs such that the paired elements are identical except for a displacement which is the same for all pairs. These element pairs define two subarrays which are identical except for a fixed known displacement.

Abstract: A merged enhancement/depletion-mode FET circuit and a complementary FET logic circuit have enhanced operation speed and reduced power dissipation. Serially connected depletion mode and enhancement mode transistors function as an output stage for the complementary FET logic stage, with the gate of an n-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage and the output of an n-channel depletion-mode transistor being connected to the common terminal or output terminal of the output stage. In an alternative embodiment, a p-channel enhancement-mode transistor is connected in parallel with the n-channel depletion-mode transistor with the gate of the p-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage. The circuitry is particularly useful in compound semiconductor circuits using MESFETS and heterojunction-FETs.

Abstract: A railroad track segment simulator for assessing track signal susceptibility to electric power line interference including a circuit including a series dc resistor, a series inductor, and an inductive network representing characteristic impedance of an electrical R-L transmission line, resistor, inductor, and network being serially connected as a series circuit, a first ballast resistance connected between one end of series circuit and a ground potential, and a second ballast resistance connected between another end of series circuit and a ground potential. The impedance of the segment is expressed as: ##EQU1## where: f=frequency (hz),r.sub.o =effective radius of rail at power line ac frequencies=0.09 m for 132 lb/yd rail,R.sub.dc =dc resistance per kft of track,j=imaginary number,Ln=impedance per track segment.A plurality of segments can be serially connected to simulate any length of line.

Abstract: An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Abstract: A network of impedance elements comprising combinations of resistors and capacitors in which the impedance of the network is modified by the selective destruction of the individual elements of the network by electrical impulses. The selective destruction of the individual elements may be planned so as to result in any combination of shorting or opening thereof.In a specific application the frequency of the oscillator used in a digital watch is adjusted by the inclusion of a network of impedance elements, wherein the elements are then selectively destroyed in accordance with measurements of the oscillator frequency to improve the precision of oscillation. This selective destruction of elements may be done automatically by electrical means, resulting in less labor, greater speed and smaller size of the oscillator, all of which are extremely important in the manufacture of digital watches. The method also simplifies the production of digital watches.

Abstract: A solid state signal generator for producing frequency combinations such as used in multi-tone telephone systems. The output of a crystal oscillator is divided to obtain binary signals proportional to the selected pairs of the seven multi-tone frequencies. These signals are scaled with selected binary output signals generated by a free-running pattern generator and representing slopes at various points on a sine wave to produce a binary signal stream that is applied to a controlled charge digital-to-analog conversion circuit that partially charges or discharges a capacitor in accordance with the binary 1's and 0's to produce an output waveform across the capacitor that corresponds to the combined pair of selected individual tone frequency sinusoids.

Abstract: A high speed driver for providing high-current and high-voltage output levels suitable for driving MOS circuits, such as MOS RAMs from standard TTL input signals. Novel circuitry in the driver provides very high speed signal switching and a power-saving feature prevents MOS supply current drain by the circuit when TTL power has been turned off.

Abstract: A central processing unit (CPU) is utilized in combination with external memories and input/output devices to form a Microcomputer System. The CPU is a 16-bit fixed word length processor monolithically integrated onto a single semiconductor chip which uses two's complement arithmetic for computations. The CPU includes an arithmetic logic unit (ALU), accumulators, data path multiplexers, program counter means, and programmable logic arrays to control operation of the processor.The processor of this invention is capable of using a homogeneous memory, wherein instructions and data are both stored in the same memory. In the disclosed embodiment, 15 of the 16-bits are used for addressing the memory. Thus, the processor is capable of directly addressing 32,768 16-bit words in the memory.An external 16-bit bus is used to interconnect the external memory and input/output devices with the CPU.

Abstract: An oxide dielectric layer is interposed between the polysilicon gate and the contact hole to the source or drain of an insulated-gate field-effect transistor to prevent electrical shorts between the gate and metal contact to the source or drain. The oxide dielectric layer enables the contact hole to be extremely close to the polysilicon gate without electrical shorts occurring therebetween, thereby eliminating the need for a minimum separation between the gate and contact hole.

Abstract: An improved charge-coupled-device gate structure utilizes three depositions of electrically conductive material to form electrodes, thereby allowing fabrication of two-phase CCD gate structures occupying less wafer surface area and operating at faster speeds than conventional charge-coupled-device gate structures.

Abstract: A video game apparatus for connection to a standard television set and including an electronics-containing console having a plurality of parameter selection buttons and a chute mechanism for receiving a replaceable cartridge-containing supplementary electronic circuitry, and a pair of hand controllers for providing player control inputs to the console electronics. Improved connector apparatus is associated with the chute mechanism to enable electrical connection to be made to a cartridge contained printed circuit board with a minimum of insertion force.

Abstract: High-speed testing circuitry which, when coupled to one terminal of a multi-terminal electronic device, such as an integrated circuit, can either supply test stimuli signals up to a frequency of 30 MHz, receive output signals produced by the device under test in response to test stimuli signals applied by associated test circuits and compare these signals against computer predicted signals, or provide for parametric testing of the device.

Abstract: The diffusivity of an impurity in a layer of polycrystalline silicon is controlled by forming the polycrystalline silicon on a thin nucleating layer of polycrystalline silicon possessing a maximum {110} texture.

Abstract: A microprocessor system having at least two separate scale integration devices. A first of the two large scale integration devices is a central processing unit formed on a single semiconductor die, and the second large scale integration device is a memory circuit formed on a separate single semiconductor die. The term "die" as used herein is conventional and refers to a unitary semiconductor body or chip. The central processing unit requires an external program counter which contains memory addresses of instruction codes to be used by the central processing unit. The memory device is electrically coupled to the central processing unit and includes a memory for storing the instruction codes, and a program counter for addressing the memory. Provision is made to incorporate additional memory circuits to expand the size and capability of the microprocessor system. System interrupt circuitry is also provided for interrupting system operation to change to a new sequence of instruction codes.

Abstract: A hand-held controller device including a two-piece outer housing shaped to be held in one hand of the user, an internal cylinder pivoted at one end and adapted to telescopically receive an elogated plunger from the other end, the plunger having a contact pin attached to the received end and a hand grip knob affixed to its other end. A first plurality of switch contacts are carried by the cylinder so as to engage a stationary contact in response to the pivotal positioning of the cylinder, and a second plurality of contact elements are also carried by the cylinder and engaged by the contact pin in response to the longitudinal positioning and the rotational positioning of the plunger.

Abstract: A programmable counter is described having three cascaded counters, the first one of which is a dual modulus prescaler. The second counter is a resettable binary counter which is fed information from a programmable read-only memory as to the numbers of times the prescaler divisions are to be repeated. The third counter is a binary counter which further divides the frequency and controls the repetition numbers delivered by the programmable read-only memory to the presettable binary counter.

Abstract: A graduated multiple collector structure for inverted vertical bipolar transistors, integrated injection logic devices and the like. The invention increases the gain of more distant collectors toward which current flows laterally past intervening collectors from a base contact, and injector or the like. The series resistance drop and the current loss in the base-emitter junction are compensated for by progressively increasing the effective area of collectors further distant from the source of the base current. Although the graduated collector structure is applicable to a wide variety of semiconductor devices, it is particularly well suited for use in oxide-isolated integrated injection logic gates. A mathematical model is provided which can help to optimize designs incorporating the graduated collector structure.

Abstract: A new and improved case for electronic wristwatch modules, which case has an improved means for activating the watch display means. The new case of this invention comprises a frame for supporting a module containing a frequency standard, a frequency divider, an electro-optical display means, and switching means for operating the display means; at least one bar retained in an edge of the frame; means for biasing the bar away from the frame; and, means coupling the bar to the switching means, whereby pressure exerted on the bar operates the display means.

Abstract: A digital circuit for sensing the signal on a data bus, selectively incrementing or decrementing the binary signal and reapplying it to the bus. The circuitry includes a binary counter comprising a temporary storage cell for each bus conductor. The output of each cell controls the conduction through an adjacent portion of a pre-charged conductor which is periodically discharged at the least significant digit cell and which, when charged adjacent a higher order cell, will inhibit the toggling of that cell. All bus lines are pre-charged to a binary "1" at a particular instant followed by the discharge to "0" of those lines whose respective cells contain a binary "0".