Abstract: A circuit for adjusting the frequency of operation of an electronic time keeping device, which device includes a source of clock pulses. The circuit of this invention is preferably located between the source of clock pulses and the time keeping device counting circuitry, so that the clock pulses can be periodically interrupted for a programmed amount of time. Accordingly, the variable adjustment capacitor, typically employed in prior art time keeping devices, can be eliminated.

Abstract: A new and improved shock-resistant electronic watch module is provided, which comprises a case, a frame of electrically insulating material mounted in the case, a lens plate of an electrically insulating material being flexibly mounted on a first side of the frame, a substrate mounted to the lens plate, a frequency standard, a frequency divider, an electro-optical display means, and means for driving the display, all being mounted to the substrate, and, a battery removably mounted on a second side of the frame and being electrically coupled to the substrate.

Abstract: A current variable shunt impedance with a non-linear control characteristic intended to functionally imitate and replace a field effect transistor responsive to a control voltage applied to its gate electrode having a source-drain path connected as a variable impedance shunt resistor in the variable frequency high pass filter section of the commercially popular Dolby B noise reduction system. The invention allows a large part of the Dolby B encode decode circuitry to be embodied in low-cost integrated circuit form while maintaining performance characteristics which closely match existing standards. These standards were previously established using noise reduction systems fabricated from discrete circuit components. The complementary nature of the encode and decode operations used to process a signal makes such matching of performance characteristics to the established standards critical.

Abstract: A method of fabricating bipolar transistors with increased gain. A base region is formed adjacent the collector (or emitter) region of the transistor, and a portion of the base region is then removed by etching. The emitter (or collector) is then formed by diffusing dopant into the base region where the portion has been removed, with the base region separating the emitter and collector having reduced thickness due to the etching. Advantageously, the base region may be formed with a more heavily-doped region overlying a less heavily-doped region, with a part of the more heavily-doped region removed by etching, thereby providing a highly conductive path to the lower conductivity base region separating the emitter and collector regions. The process steps are compatible with conventional integrated-circuit fabrication processes.

Abstract: An improved circuit for a band gap voltage regulator is provided with a merged reference voltage source and error amplifier wherein the circuit operates simultaneously as a generator of the internal reference voltage as well as the small signal error amplifier for comparing a fraction of the output voltage to the reference voltage.

Abstract: An improved method and structure for producing narrow openings to the surface of a first material possessing a first set of etch characteristics is disclosed. The method includes the step of forming on a portion of the surface of the first material an etchable mask having a first narrow-opening-forming lateral edge disposed along a selected edge of the to-be-formed narrow opening. A protective layer of a second material possessing a second set of etch characteristics is next formed on the exposed surface of the first material, the protective layer having a second narrow-opening-forming lateral edge juxtaposed the first narrow-opening-forming lateral edge. The first narrow-opening-forming lateral edge on the mask is then etched to expose unprotected areas of the first material thereby producing the narrow opening to the surface of the first material. The method and structure of the invention is particularly well suited for producing fine geometry patterns in solid state device structures.

Abstract: An improved method for producing a plurality of closely-spaced altered regions in the surface of a first material possessing a first set of etch characteristics is disclosed. The method includes the steps of forming an etchable mask of a second material over a portion of the first material, which mask has a second set of etch characteristics and a lateral edge disposed along a selected edge of a first of the to-be-altered closely-spaced regions in the first material. A protective layer of a third material possessing a third set of etch characteristics is next formed on the exposed surface of the first material, the protective layer having a second lateral edge juxtaposed the first lateral edge. The first lateral edge of the mask is then etched to expose unprotected portions of the first material. The exposed unprotected portions of the first material are then altered by either etching or diffusion.

Abstract: A device for forming reference axes on an image sensor package containing an image sensor array. The device comprises an optical means having a reticle formed therein, a movable table located in a plane parallel with the plane of the optical means, a scribe mounted between the movable table and the optical means and movable in a direction parallel with the reticle.

Abstract: Thermoprocessing of integrated-circuit devices and ionizing radiation environments create electronic charges in dielectric isolation materials and in dielectric-semiconductor interface regions. These charges can produce serious alterations in the operating characteristics of the devices and integrated circuits. The deleterious effect of these charges may be greatly reduced by the disclosed process which produces a single-crystal silicon film dielectrically isolated from a polycrystalline silicon support by an underlying insulator of either silicon nitride or silicon dioxide, both of which may be grown by the process at selected locations on the same chip.

Abstract: A new and improved voltage multiplier circuit is provided which converts a relatively low voltage to a relatively high voltage without any undesirable voltage drops across any of the constituent components. A plurality of the disclosed voltage multiplier circuits may be cascaded together to increase the multiplied output voltage, wherein each multiplier stage of the cascaded circuits multiplies the input voltage by two.

Abstract: A semiconductor structure for, and method of manufacture of, a linear integrated circuit provides the equivalent of a base function in a transistor, wherein the base function has a dual charge density, with the latter being relatively low in the lower active area of the base between PN junctions for high gain and high breakdown voltage, but high along the upper surface to prevent an unwanted inversion layer from occurring.

Abstract: An RF oscillator and modulator produces a stable moudlated RF signal with a varying voltage source and without the requirement for critical device selection. A bias voltage for the oscillator transistor is provided by diode means at the oscillator output, the bias voltage being commuted to the transistor through the oscillator tuned circuit. Advantageously, the diode means biases a diode modulator connected to the oscillator output and to a modulation signal whereby linear operation of the diode modulator is enhanced.

Abstract: A very high-speed exclusive OR/NOR circuit in which output function and its complement are propagated simultaneously. Developed particularly for use in integrated circuit applications, the basis circuit uses six NPN transistors in a tree configuration to select one of four mutually exclusive conductive paths which correspond to the four states of the truth table of a two-variable exclusive OR/NOR function.

Abstract: An AC to DC voltage converter provides both regulated and unregulated voltage from the positive DC voltage output terminal which is connected to a power input terminal of a load. One load circuit is returned to a common circuit terminal (e.g. ground) and another load circuit is returned to the converter whereby the regulator is by-passed.

Abstract: A memory cell is provided which comprises a word line, a current source line, a pair of bit lines, a first transistor having a base terminal, a collector terminal coupled to the word line, a first emitter coupled to a first of the pair of bit lines, a second emitter coupled to the current source line, a second transistor having a base terminal coupled to the collector terminal of the first transistor, a collector terminal coupled to the word line and to the base of the first transistor, a first emitter coupled to a second of the pair of bit lines, and a second emitter coupled to the current source line, and means for directing more current through the second transistor than through the first transistor.

Abstract: A device for introducing a known amount of charge to a line of charge storage elements in a charge-coupled device fabricated in a conductor-insulator-semiconductor system includes a buffer charge storage element fabricated adjacent a first charge storage element in the line of charge storage elements, the buffer charge storage element having its gate electrode controlled by a logic pulse whose level determines whether charge is to be introduced to the line of charge storage elements, and precharge means coupled to this buffer charge storage element for supplying a saturating charge to the buffer charge storage element.

Abstract: An improved memory cell comprising a word line, a pair of bit lines, a pair of load impedances, and a pair of switching transistors. The pair of switching transistors each include an emitter coupled to a respective one of the bit lines, a base coupled to a respective one of the load impedances, and a collector coupled to the base of the other switching transistor. The pair of load impedances may include a pair of transistors each having an emitter coupled to the word line, a base coupled to a respective one of the emitters of the pair of switching transistors, and a collector coupled to a respective one of the bases of the switching transistors.

Abstract: An improved method of MOS circuit fabrication includes the consecutive steps of formation of a selected material on the surface of an underlying substrate, removal of the selected material from selected portions of the underlying substrate, and formation of insulating material between the selected material and the underlying substrate on the surface of the newly exposed underlying substrate.

Abstract: A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Q.sub.ss in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.

Abstract: A process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases in a semiconductor substrate utilizes the stopping power of different layers of materials to determine the location of impurity concentrations induced by ion implantation.