Abstract: A communication system for deaf, deaf-blind, or non-vocal individuals includes an instrumented glove for obtaining electrical signals indicative of a hand configuration of a first individual. Strain gage sensors in the glove flex with movement of the hand. Each sensor includes a tension strain gage and a compression strain gage which are serially connected and form two legs in a bridge circuit. Signals from the bridge circuit are amplified and digitized and applied to a computer which includes an adaptive pattern recognition algorithm which is responsive to hand-state vectors for recognizing letter beacons in hand-space. A second individual communicates with the first individual through the computer system using a portable keyboard. The output devices for communicating to the first and second individuals depend on the visual, vocal and hearing capabilities of the individuals and can be selected from a voice synthesizer, LCD monitor, or braille display.

Abstract: The access time in reading data from a read only memory is enhanced by selectively inverting data stored in the memory. Each storage location along a wordline is weighted according to the distance of the bit location from the wordline driver, and bits stored therein are weighted by the bit location weight. The total weights of bits stored along the wordline are summed and compared with the maximum possible sum of weighted bits. If the ratio exceeds a preselected value, all bits of the wordline are inverted. The wordlines of a memory are provided with flag bits to indicate whether or not data stored on the wordline has been inverted.

Abstract: A programmable logic device having greater design flexibility through use of a plurality of programmable macrocells in conjunction with programmable gate arrays. Each macrocell includes a programmable reconfigurable register for receiving sum terms from the array, and an I/O terminal connected to receive an output from the programmable reconfigurable register. Two separate feedbacks from the macrocell to the gate array are provided. The first feedback has multiple inputs including the register output, and the second feedback has multiple inputs including the I/O terminal. Accordingly, the I/O terminal and the register can function independently.

Abstract: Apparatus for washing the disc portions of an electrical insulator includes first and second mating housing portions for positioning about the discs and fluid lines for delivering a cleansing fluid through the housing portions for cleaning the surface of the discs. The two mating housing portions preferably define a basin for collecting the cleansing fluid and facilitating removal of the cleansing fluid after use. A support assembly including a robotic arm positions the first and second mating housing portions about the discs of the electrical insulator for cleaning. A cleaning liquid such as water or freon or a cleaning gas such as air or steam is applied through the mating housing portions for cleaning the surface of the discs. Following the cleaning, a surface-enhancing material such as a silicone coating can be applied to the surface of the insulator for protection from future contamination and make the insulator more resistant to electrical or mechanical degradation.

Abstract: The interface of a silicon oxide passivation layer and a silicon substrate in a silicon solar cell is stabilized by covering the silicon oxide passivation layer with a layer of undoped or phosphorus doped polycrystalline silicon. A second layer of silicon oxide is formed by deposition on the surface of the phosphorus doped polycrystalline and enhances the anti-reflection characteristics of the composite structure.

Abstract: A CBiCMOS transmission gate in which the sources of a CMOS transistor pair are connected to an input and the drains are connected to the bases of a complementary bipolar transistor pair. The bipolar transistor pair is serially connected between a plus voltage potential and ground whereby a logic one applied to the input is transmitted through the PMOS transistor to the base of an NPN transistor which applies the plus voltage to an output terminal, and a logic zero applied to the input is transmitted to the NMOS transistor to the base of a PNP transistor to apply ground to the output terminal.

Abstract: Voltage on a circuit ground terminal in an output buffer is controlled by limiting induced voltage on a circuit ground pad as the output makes a transition from a high voltage level to a low voltage level thereby minimizing deleterious effects on other circuits connected to the common circuit ground terminal. A ground bounce circuit controls the bias on a transistor connecting the output to the circuit ground terminal with power saver circuitry limiting actuation of the ground bounce circuitry except during the high to low transitional phase.

Abstract: An RF power device including a DMOS field effect transistor has increased efficiency and reduced distortion. A capacitor is connected between the gate and source input of the transistor which swamps non-linear variations of the parasitic capacitance (C.sub.GD) between the gate and drain, thereby offsetting the Miller effect of the feedback provided by the MOS transistor parasitic capacitance. The capacitor, the Ciss of the MOS transistor, and the inductance of input leads provide a device input resonant frequency between the input signal fundamental frequency and the first harmonic.

Abstract: Magnetic resonance signals for imaging species having short spin-spin relaxation times (T.sub.2) are obtained without the need for a refocusing lobe. A series of RF excitation pulses are applied to the species with magnetic resonance signals being detected after each RF excitation pulse is applied. The magnetic resonance signals are then combined to provide the imaging signals. In one embodiment, each RF excitation pulse is half of a conventional slice-selective pulse with each pulse being slewed to zero.

Abstract: An optically pumped semiconductor laser comprises multiple asymmetric quantum well structures. Using the structures described herein, the selection rules for additional optical transitions can be made possible and three or four level lasers can be obtained. A population inversion can be achieved by optical pumping for lasing for those not allowed in a simple quantum well.

Abstract: Thermal balance in an array of RF transistor cells in which all transistors are connected in parallel is obtained by interconnecting the transistors to array contacts by means of discrete wire leads. The array is electrically tested and a temperature distribution in the array is obtained. Thereafter, the wire leads are varied in length and height above the plane of the array to improve temperature distribution during test. The steps are repeated as necessary to obtain a desired temperature balance in the array.

Abstract: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Abstract: An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common control gates. A third n-type floating gate field effect transistor is utilized for programming the memory cell. The floating gate and the control gate of the third transistor are connected to the common floating gates and the common control gates, respectively, of the Complementary Metal Oxide Silicon (CMOS) transistor pair. The memory cell is tri-statable by connecting the source of the p-channel transistor of the Complementary Metal Oxide Silicon (CMOS) pair to the common control gates.

Abstract: Hot-carrier suppression in a sub-micron MISFET structure is achieved by providing a drain region which includes a steeply profiled N+ (or P+) doped region in the surface of a semiconductor body with a first epitaxial layer formed thereover having N- (or P-) dopant concentration. A second N+ (or P+) epitaxial layer is formed over the first epitaxial layer and functions as a low ohmic contact to the drain region. In a preferred embodiment both the source and drain regions have dopant concentrations provided by N+ (or P+) doped regions in the surface of a substrate with epitaxial layers thereover. The dopant profile reduces the voltage drop across the more highly doped region of the drain and thereby reduces the electric field therein. Further, the reduction in dopant concentration reduces the electric field due to energy band bending associate with the change in doping level from the N+ (P+) region to the N- (P-) epitaxial layer. The resulting sub-micron device has better long-term reliability.

Abstract: The performance of a silicon photovoltaic cell is improved while process yield is maintained by first forming doped regions in a major surface of a silicon wafer and providing electrical interconnections to the doped regions prior to thinning the wafer by etching another major surface of the wafer. A passivating antireflection layer is applied to the etched surface after the surface is precleaned. The precleaning can be by ammonia plasma applied in situ as a precursor to depositing silicon nitride as the passivation layer.

Abstract: Memory address generation circuitry includes two binary counters for generating addresses for application to an address bus. The least significant bits of one counter are connected to the address bus in bit positions corresponding to the most significant bits of the other counter whereby the two counters increment addresses in opposite directions. The mode of address generation permits addresses for data in normal order, data within data blocks in normal order and data blocks in reverse-bit order, and data within data blocks in bit-reverse order and data blocks in normal order. The circuitry has particular applicability in memory address generation when operating on data with algorithms for FFT operations in one or more dimensions.

Abstract: Disclosed is a method of obtaining magnetic resonance signals from a body which are spatially and spectrally selective comprising the steps of applying a static magnetic field (Bo) to said body thereby aligning nuclear spins, applying a modulated magnetic gradient (G(t)) to said body, applying an RF excitation pulse (B(t)) to said body to tip said nuclear spins, said RF excitation pulse being related to said modulated magnetic gradient whereby resulting magnetic resonance signals are spatially and spectrally dependent, and detecting said magnetic resonance signals. The steps can be repeated in a multi-slice or multi-spectral acquisition mode. The steps can be repeated in a rapid gradient echo pulse sequence.

Abstract: A two-dimensional projection image of the NMR activity within a volume is obtained. The signals due to static material are not excited and do not appear in the projection image. The signals due to moving blood in vessels produce an isolated image of the vessels with the superimposed structure removed. Excitation systems are used which excite only moving material and return static material to equilibrium.

Abstract: A method of obtaining multi-dimensional spatially-selective magnetic resonance signals from a body includes applying a static magnetic field (Bo) to said body thereby aligning nuclear spins along an axis (z), and applying one or more time-varying magnetic gradients (Gx(t), Gy(t), Gz(t)) during a time period, T. During the time period, T, an RF excitation pulse (B.sub.1) is applied to said body to tip said nuclear spins, said RF excitation pulse being related to said modulated magnetic gradients by a first spatial frequency weighting function (W(k)(t)) whereby magnetic resonance signals transmitted by said tipped nuclear spins are spatially selective in multi dimensions. The resulting magnetic resonance signals are then detected to provide the multi-dimensional spatially-selective signals.

Abstract: A method of interconnecting circuit components in a semiconductor integrated circuit including component elements formed in the substrate and thin-film resistors and capacitors formed on a surface of the substrate, a molybdenum plug is utilized to facilitate stable, uniform low resistance contacts to circuit elements, molybdenum (moly) plugs are utilized as a barrier between interconnect metallization and the circuit components. A CLAD moly/aluminum metallization interconnect can be fabricated in a standard process in which the moly plugs are formed. The accuracy and stability of thin-film resistors is facilitated during wafer processing, laser trimming, temperature cycling, and assembly processing thereby providing repeatable matching by eliminating contact resistance as a process variable.