Abstract: The location of underground objects such as pipes and conduits are located by detecting electrical signals emitted by the underground objects where the radiated signals include spread spectrum modulated RF signals. The system can operate in a passive or active mode, and in the active mode pseudo-noise (PN) generators can be employed or frequency-hopping can be employed. The use of spread spectrum minimizes or eliminates conflicting signals radiated from a plurality of underground objects and can improve signal to noise ratio of the detected signals.

Abstract: A current mirror bias circuit for an RF amplifier transistor is modified whereby the reference transistor of the current mirror tracks hot carrier degradation in the RF transistor. Gate bias to the current mirror transistor is modified whereby the drain-to-gate voltage can be positive, and the lightly doped drain region in the lateral n-channel reference transistor is shortened and dopant concentration increased to increase the electric field of the reference transistor to provide the hot carrier injection degradation characteristics similar to the main transistor. Additionally, the gate length of the reference transistor can be shortened to effect the hot carrier injection degradation.

Abstract: Disclosed is an apparatus and a method for three dimensional magnetic resonance data acquisitions using a fast 3D sequence to acquire volumetric data in a cine mode. The entire heart can be imaged in the same amount of time that a conventional cine scan requires for a single section. The true temporal resolution is similar to that of the segmented k-space acquisition. The sequence uses very short repetition times (TR), and hence the inherent contrast is poor. This problem is overcome with the use of a T1 shortening agent. Since contrast between blood and the myocardium is no longer flow dependent, it is more stable throughout the heart cycle.

Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated circuit package and having a plurality of holes for receiving leads extending from the package. A second member has a plurality of wire contacts for engaging the leads, the first and second members being arranged to permit relative lateral translation thereof. A cam is provided for sliding the first member relative to the second member and moving leads extending through the holes in the first member into engagement with the contacts of the second member. A socket for dual in-line integrated circuit package (DIP) has two rows of holes in the first member, and two slots are provided in the second member each aligned with a row of holes. The wire contacts extend across each slot. For high temperature operation (greater than 250° C.) the first and second members comprise anodized aluminum or a ceramic, and the wires comprise Monel or other high temperature material.

Abstract: A method of forming high quality inductors and capacitors in semiconductor integrated circuits utilizes one or more sealed air-gaps in a supporting substrate under the passive devices. The process is compatible with standard silicon processing and can be implemented with high temperature processing at the beginning, middle, or end of an integrated circuit fabrication process. A one micron air-gap in a high resistivity epitaxial layer results in a parasitic capacitance equivalent to 3.9 micron thick silicon oxide or a 11 micron thick depletion layer in silicon.

Abstract: A method of using static power supply current in response to test vectors for acceptance testing and defect diagnosis of CMOS integrated circuit die. Testing is based on comparison of two or more power supply current measurements from the die under test. Defect diagnosis is based on characterizing a defect by one or more current levels produced by the circuit in the presence of the defect.

Abstract: A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.

Abstract: Susceptibility artifacts in slice selective volume magnetic resonance spectroscopy are reduced by applying phase encoding at a nominal resolution equal to or larger than the slice selection dimensions. In a preferred embodiment of the method, phase encoding is applied along the axes of the first and last RF slice selections. The volume of interest is contained completely within a single pixel defined by the 2D phase encoding. Unsuppressed water reference signal from the volume of interest is relatively unaffected by these artifacts and is collected without phase encoding.

Abstract: A signal function S(t.sub.1, t.sub.2) is obtained from a plurality of coherence transfer pathways in a single acquisition by preparing a molecular system in a coherent non-equilibrium state, and alternately and sequentially detecting signals at individual sampling points, in t.sub.2, from the plurality of coherence transfer pathways by using gradient refocusing of a new pathway after siganl detection at a sampling point in another pathway. The gradient encoding and refocusing of coherence pathways can use inhomogeneous rf-pulses (B.sub.1 gradients) or B.sub.0 field gradients. The coherence transfer pathways can be sequentially selected in an arbitrary order.

Abstract: Control of a split screen display and the display of sequential images on a display is effected by rotation of a trackball. Pulse trains generated by rotation of the trackball are inputted to a microprocessor which controls the junctions in a split screen and the image data applied to a display.

Abstract: In a magnetic resonance imaging system, an RF power amplifier is employed to boost an RF pulse to sufficient strength to excite the nuclear spins in a subject. The non-ideal behavior of the amplifier distorts the shape of an excitation pulse, and this distortion in turn degrades a slice profile. The distortion of the RF signal is manifested by nonlinearity in amplification and in incidental phase modulation. By determining the amount of nonlinearity and the phase modulation resulting from the power amplification, the baseband RF signal can be predistorted or prewarped to offset the distortion resulting from amplification. Improved slice selectivity results therefrom.

Abstract: A low profile flexible microwave radiating array includes a base structure on which are positioned a plurality of rigid platforms which support individual antenna elements. In one embodiment the support platforms are generally cubical in configuration with the antennas being fabricated as microstrip radiators which are bonded to one surface of the cube. A coaxial connector is provided to energize the antenna. The rigid platforms maintain the desired spacing and orientation between the antenna and the skin of a patient, and the individual platforms and the flexible base permit the blanket to conform with complex surfaces on a patient.

Abstract: The performance of current, flow-based sequences for imaging vasculature using MR is severely restricted in regions with inherently slow flow. We address this problem with a flow-independent imaging method. Specifically, we generate projection images of blood in the limbs while suppressing signals from all other tissues (primarily skeletal muscle, bone marrow, and subcutaneous fat) using a flow-compensated, water-selective, short TI inversion recovery sequence with a long echo time. We experimentally evaluate the effectiveness of this sequence and present in vivo results clearly demonstrating the method's potential.

Abstract: A memory matrix comprises a plurality of word lines, a plurality of bit lines, and a stacked diode and voltage-variable resistor structure interconnecting bit lines to word lines. The stacked diode and voltage-variable resistor structure includes a doped region in a semiconductor substrate defining a work line, a doped polycrystalline silicon layer over said word line and forming a p-n junction therewith, and an amorphized region in the doped polycrystalline silicon layer having increased resistance over the non-amorphized portion of the doped polycrystalline silicon layer. A contact is made to the amorphized polycrystalline silicon material which preferably includes a titanium-tungsten barrier layer and an aluminum layer over the barrier layer.

Abstract: This is an invention for a complementary transistor pair which includes an n-channel double-diffused-metal-oxide-semiconductor transistor having a source, a drain and an insulated gate. A Schottky barrier junction diode is formed to the drain of the n-channel transistor. The transistor pair also includes a p-channel double-diffused-metal-oxide-semiconductor transistor which also has a source, a drain and an insulated gate. A second Schottky barrier junction diode is formed to the drain of the p-channel transistor. The two Schottky diodes are electrically coupled to one another.

Abstract: Polysilicon contacts for silicon devices such as bipolar junction transistors and silicon solar cells are fabricated in a two step anneal process to improve contact resistance and emitter saturation current density. After a silicon oxide layer is formed on a surface of a silicon substrate, a plurality of openings are formed there through to expose a plurality of contact surfaces on the surface of the silicon substrate. A thin thermally grown silicon oxide layer is then formed on the contact surfaces after which an undoped layer of polysilicon material is formed over the silicon oxide layers. The structure is then annealed at approximately 1050.degree. C. to break the thermally grown silicon oxide layer. Thereafter, a first layer of doped glass is formed over the silicon oxide surface and selectively etched to remove the first layer of glass from a first group of contact surfaces. A second layer of doped glass is then formed over the first group of contact surfaces and over the first layer of doped glass.

Abstract: A discrete cosine transform/inverse discrete cosine transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.

Abstract: An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands.

Abstract: A body having a surface for facilitating liquid adherence includes a substrate and a layer of etchable material on a surface of the substrate. Grooves having re-entrant surfaces are formed in the layer of material. In one embodiment, a heat sink for a semiconductor integrated circuit includes a heat-conducting body having a major surface and a grooved layer of a polymer on the major surface. The layer of polymer is encased in a metal layer which provides strength and electrical and thermal conductance. Reactive ion etching can be employed to form the grooves in the polymer, and metal sputtering and electroless plating can be employed to form a composite metal layer.

Abstract: A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.