Patents Represented by Attorney Henry K. Woodward
  • Patent number: 6351128
    Abstract: Resistivity mapping apparatus includes a tow mechanism for use by a human operator in moving the mapping apparatus over a surface and measuring the resistivity of soils of the surface. The tow mechanism includes a generally triangular shaped tow ring which is engageable by the operator's battery belt, harness, or pack-frame, the tow ring having two opposing hooks at a vertex of the tow ring for receiving a loop from a tow line. The tow line engages the tow ring and a cable depressor weight which keeps the resistivity mapping apparatus in close proximity to the earth as the apparatus is towed. A communication cable in the tow line preferably comprises an optical fiber which transmits signals from the receiver to a data logger carried by the operator.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: February 26, 2002
    Assignee: Geometrics
    Inventor: Jeffery M. Johnston
  • Patent number: 6333457
    Abstract: Edge passivation for a small area silicon cell is provided in a batch process by providing streets between individual cells formed in a silicon substrate and diffusing dopant through the substrate along the streets. Following completion of fabrication of the plurality of cells in the substrate, the substrate is sawed along the streets with the diffused region providing passivation along the edges of the individual die.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: December 25, 2001
    Assignee: SunPower Corporation
    Inventors: William P. Mulligan, Pierre J. Verlinden
  • Patent number: 6326849
    Abstract: In an RF amplifier circuit having a plurality of transistor stages with each transistor having an input terminal for receiving an RF signal, a bias circuit is provided for applying a DC bias to the input terminal of a transistor. An isolation circuit connects a DC power supply to a bias circuit whereby DC voltage from the power terminal is applied to the bias circuit and RF signal from the transistor input terminal is attenuated. The isolation circuit includes a reactive serial path which allows the flow of DC current and presents an impedance to RF current flow and a reactive shunt path to ground which can comprise a capacitor or a serial inductor/capacitor circuit. The reactive serial path can comprise an inductor or an inductor/capacitor parallel circuit.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: December 4, 2001
    Assignee: EiC Corporation
    Inventors: Nanlei Larry Wang, Shuo-Yuan Hsiao, Wei-Shu Zhou, Shihui Xu
  • Patent number: 6319799
    Abstract: A heterojunction transistor with high mobility carriers in the channel region includes a source region and a drain region formed in a semiconductor body with the source region and the drain region comprising doped semiconductor alloys separated from the substrate by heterojunctions. A channel region is provided between the source region and the drain region comprising an undoped layer of an alloy of the semiconductor material and a deposited layer of material of the semiconductor body overlying the undoped layer. A gate electrode is formed on a gate oxide over the channel region. In fabricating the high mobility heterojunction transistor, the spaced source and drain regions are formed in the substrate by implanting dopant of conductivity type opposite to the substrate and a material in the alloy and then annealing the structure to form the alloy of the semiconductor material under the undoped layer.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: November 20, 2001
    Assignee: Board of Regents, The University of Texas System
    Inventors: Qiqing Ouyang, Al F. Tasch, Jr., Sanjay Kumar Banerjee
  • Patent number: 6313395
    Abstract: An interconnect structure for use with solar cells and like devices which are subject to compressive and/or expansive forces through packaging or in application comprises a flattened spiral of a metal strip. The interconnect is fabricated by first providing a length of metal strip, wrapping the metal strip around a cylindrical or flat mandrel or otherwise folded in a helical pattern, removing the mandrel, and then flattening the metal strip to reduce thickness of the interconnect.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: November 6, 2001
    Assignee: SunPower Corporation
    Inventors: Richard A. Crane, Matthew B. Piper, Shandor G. Daroczi
  • Patent number: 6313487
    Abstract: A vertical channel flash memory cell with a silicon germanium layer in the channel region provides enhanced secondary electron injection when programming the device. The device includes a silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer. A sidewall through the stacked structure is formed by etching thereby exposing edges of the silicon layer and the silicon germanium layer and a portion of the substrate. A floating gate is formed overlying the sidewall and insulated therefrom with a control gate overlying the floating gate and insulated therefrom. A source region is formed in the silicon layer and a drain region is formed in the substrate with a channel therebetween along the sidewall and including the silicon germanium layer. The silicon germanium layer is preferably compressively strained and can have a uniform mole fraction or a graded mole fraction.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: November 6, 2001
    Assignee: Board of Regents, The University of Texas System
    Inventors: David L. Kencke, Sanjay K. Banerjee
  • Patent number: 6313486
    Abstract: A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: November 6, 2001
    Assignee: Board of Regents, The University of Texas System
    Inventors: David L. Kencke, Sanjay K. Banerjee
  • Patent number: 6305975
    Abstract: An electrical feedthrough connector to a low pressure (vacuum) chamber such as in a mass spectrometer comprises an epoxy body having at least two generally cylindrical portions with a step between the two generally cylindrical portions and with the portions mating with circular openings in the housing for the low pressure chamber. A step between the two cylindrical portions of the electrically insulating body mates with a step in the opening in the chamber housing with a gasket such as an o-ring placed between the steps to provide a pressure seal. A rigid printed circuit board with electrical components for an interconnect circuit is affixed to one end of the electrically insulating body with a flexible printed circuit connector extending from the rigid printed circuit board through the epoxy body to the low pressure chamber for interconnecting components within the chamber.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: October 23, 2001
    Assignee: Bear Instruments, Inc.
    Inventor: Urs Steiner
  • Patent number: 6307368
    Abstract: A fast, spectrally-selective steady-state free precession (SSFP) imaging method is presented. Combining k-space data from SSFP sequences with certain phase schedules of radiofrequency excitation pulses permits manipulation of the spectral selectivity of the image. For example, lipid and water can be rapidly resolved. The contrast of each image depends on both T1 and T2, and the relative contribution of the two relaxation mechanisms to image contrast can be controlled by adjusting the flip angle. Several applications of the technique are presented, including fast musculoskeletal imaging, brain imaging, and angiography. The technique is referred to herein as linear combination steady-state free precession (LCSSFP) and fluctuating equilibrium magnetic resonance (FEMR).
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: October 23, 2001
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Shreyas S. Vasanawala, John M. Pauly, Dwight G. Nishimura
  • Patent number: 6300649
    Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: October 9, 2001
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
  • Patent number: 6297700
    Abstract: The power delivered by an RF power transistor having cascaded cells or unit elements is improved by reducing the phase imbalance between elements and thereby reducing transverse effects between cells. Phase imbalance is reduced by varying the number of transistor elements connected to interconnect areas, connecting wire bonds to an input transmission line concentrated near an outer edge in the transmission line to take advantage of surface skin effects on current, and varying the surface area of the interconnect areas to adjust input impedance and output impedance of each cell.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: October 2, 2001
    Assignee: UltraRF, Inc.
    Inventors: John F. Sevic, Christopher J. Knorr, James R. Parker, Howard D. Bartlow
  • Patent number: 6268728
    Abstract: Inhomogeneity of the radio-frequency (RF) field B1 interferes with imaging methods such as fat saturation which are sensitive to variations in the tip angle achieved by an RF pulse. In addition, in the common case in which the MR signal is received through the same coil used for excitation, the RF field is a measure of the receiver coil sensitivity. If the RF field can be measured, RF pulses could be designed specifically to counteract the inhomogeneity of the RF field. Additionally, maps of the RF field could be used as coil sensitivity maps, which may be used for image intensity correction. A phase-sensitive method of B1 mapping is presented which is applicable over a wide range of RF inhomogeneity corresponding to flip angles ranging from about 45 to 135 degrees. This method requires two or three acquisitions in addition to the acquisition of a main-field (B0) field map.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: July 31, 2001
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventor: Glen Morrell
  • Patent number: 6259273
    Abstract: An improved programmable logic device comprises a mixed mode programmable logic array in which a group of product terms generated by a programmable AND array are both fixedly connected to a group of OR gates and selectively connected to a programmable OR array. All the outputs of the OR gates and the programmable OR array are fed to a programmable multiplexer which provides a set of outputs of the device. The OR array is split into two sub OR arrays connected by a programmable OR array connection bit line to offer more flexibility. This structure mixes programmable OR array and fixed OR array together and provides the device with fast speed performance as well as high logic mapping flexibility and logic utilization.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: July 10, 2001
    Assignee: ICT Acquisition Corp.
    Inventors: Peter Yiyian Yin, Ping Xiao
  • Patent number: 6249137
    Abstract: A test circuit for applying bipolar current pulse to first and second terminals of device under test (DUT) includes a first DC current source and a first switch having a first common terminal, a second DC current source and a second switch having a second common terminal, and means for connecting a device under test between the first and second common terminals. A timing generator selectively controls conduction of the first switch and the second switch whereby when the first switch is closed the current from the second DC current source flows through the device under test and the first switch to a circuit ground, and when the second switch is closed the current from the first DC current course flows through the device under test and the second switch to a circuit ground. Pulse repetition rate and duty cycle of the current pulses are controlled by the control voltage pulses from the timing generator.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: June 19, 2001
    Assignee: Qualitau, Inc.
    Inventors: Gedaliahoo Krieger, Yongbum Cuevas
  • Patent number: 6236738
    Abstract: Disclosed is a method for nonrigid cyclic motion analysis using a series of images covering the cycle, acquired, for example, from phase contrast magnetic resonance imaging. The method is based on fitting a global spatiotemporal finite element mesh model to motion data samples of an extended region at all time frames. A spatiotemporal model is composed of time-varying finite elements, with the nonrigid motion of each characterized by a set of Fourier harmonics. The model is suitable for accurately modeling the kinematics of a cyclically moving and deforming object with complex geometry, such as that of the myocardium. The model has controllable built-in smoothing in space and time for achieving satisfactory reproducibility in the presence of noise. Motion data measured, with PC MRI for example, can be used to quantify motion and deformation by fitting the model to data.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: May 22, 2001
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Yudong Zhu, Norbert J. Pelc
  • Patent number: 6233628
    Abstract: A computer system includes a host computer and a peripheral memory device such as a CD ROM which are interconnected by a bus including a plurality of pipes defined by packets, time division multiplexing, frequency division multiplexing, or code division multiplexing. A plurality of pipe configuration registers are maintained for controlling bus configuration. A BUS controller for the bus includes a plurality of registers for controlling data transfer including pipe data flow direction, packet size, control information, bandwidth setting, and descriptor pointer. The plurality of pipes can have different bandwidths and latencies to efficiently facilitate the transfer of commands, data, and control information. The peripheral memory device is able to transfer and receive data directly to and from the host computer using a dedicated pipe without the need of a buffer memory at the peripheral device.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: May 15, 2001
    Assignee: Oak Technology, Inc.
    Inventors: Dan Salmonsen, Steven E. Olson, Ning (Eric) Zhou
  • Patent number: 6229337
    Abstract: A high-density programmable logic device is presented, comprising two or more logic built-in blocks interconnected by a programmable global interconnect multiplex matrix. Each logic built-in block contains four groups of four macrocells and four I/O cells, two sub AND arrays and four sub OR arrays. Each sub OR array couples a group of macrocells, and each sub AND array drives two sub OR arrays. The sub AND and OR arrays can either function independently or be connected together by AND array or OR array connection facilities, to extend the logic capability. Every macrocell can be flexibly controlled by three levels of control signal: global, logic built-in block wide or separate. The outputs from the macrocells and the inputs from I/O cells can be fed locally back through the local feedback path, and also fed globally to other logic built-in blocks, through the global interconnect multiplex matrix.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: May 8, 2001
    Assignee: ICT Acquisition, Inc.
    Inventors: Ping Xiao, Yiyian P. Yin
  • Patent number: 6219571
    Abstract: A new technique for imaging a material with a high T2/T1 ratio such as articular cartilage uses driven equilibrium Fourier transform (DEFT), a method of enhancing signal strength without waiting for full T1 recovery. Compared to other methods, DEFT imaging provides a good combination of bright cartilage and high contrast between cartilage and surrounding tissue. Both theoretical predictions and images show that DEFT is a valuable method for imaging articular cartilage when compared to spoiled gradient recalled acquisition in the steady-state (SPGR) or fast spin echo (FSE). T2-decay, T1 recovery, echo time, magnetization density, proton density, and equilibrium density per proton are related by a derived equation.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: April 17, 2001
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Brian A. Hargreaves, Dwight G. Nishimura
  • Patent number: 6215152
    Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: April 10, 2001
    Assignee: CREE, Inc.
    Inventor: Francois Hebert
  • Patent number: 6215306
    Abstract: The quality of spiral images depends on whether actual k-space sampling points are at their nominal positions. Although newer gradient systems can provide more accurate gradient waveforms, timing mis-registration between data acquisition and gradient systems can significantly distort the positions of samples. Even after the timing of data acquisition is tuned, minor residual errors can still cause shading artifacts which are problematic for quantitative MRI applications, such as the phase-contrast method. Although ideally measuring the actual k-space trajectory can correct for the timing errors, it requires additional data acquisition and scan time. The present invention employs off-centered spiral trajectories which are more robust against timing errors and applies them to the phase-contrast method. The new trajectories turn shading artifacts into a slowly-varying linear phase in reconstructed images without affecting the magnitude of images.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: April 10, 2001
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Chi-Ming Tsai, Lai-Chee Man