Abstract: An integrated circuit junction capacitor is formed using conventional bipolar transistor technology. Voltage variable capacitance is provided by a reverse biased emitter-base junction and parasitic collector-base capacitance is isolated from the emitter-base capacitance by maintaining the base-collector junction in a reverse biased condition. A bootstrapped driver circuit is also described in which bootstrap current is provided by a transistor-like structure in which an internal load capacitance enables circuit performance to remain substantially constant under various driven load conditions.

Abstract: A technique for providing interconnections between pairs of contact points associated with a conductive line pattern by the use of an interconnection defining tool which is selectively alignable with respect to the conductive line. The conductive line pattern comprises at least one conductive line which is either continuous or shows interruptions, and from which lines branch off to the contact points. The tool is adapted to the conductive line and consists of a row of elements, the distance between which is dimensionally related to the distance between the branch-offs. After the tool has been adjusted to the conductive line in accordance with the respective connections, the elements of the tool are used for interrupting or connecting the conductive line at predetermined positions.

Abstract: A high performance semiconductor memory read/write data access circuit including a sense amplifier directly coupled to a pair of bit lines is provided with a pair of bit switching devices to enable data communication external to the memory. Control potentials and timing of switching signals are provided in such a manner that only one of the bit switches becomes conductive during reading and writing access to the memory.

Abstract: The invention disclosed pertains to a method for the manufacture of an integrated insulated gate field effect transistor semiconductor device wherein a silicon gate structure is simultaneously formed with a composite layer of silicon and a conductive silicide forming metal which upon subsequent annealing forms a conductive metallic silicide compound within the via interconnection means. The aforesaid structure is accomplished utilizing a photoresist lift-off technique as a masking material as well as a substance per se or in combination with other materials to define evaporative conductive metal dimensions on a diffused silicon substrate.

Abstract: A method is presented for accelerating the injection of minority carriers into an insulating layer overlying a semiconductor substrate under conditions less severe than required to produce impact ionization. The method is useful in characterizing parameters of field effect integrated circuit components subject to various charge instability mechanisms and may also be useful as a means for altering charge conditions in various non-volatile memory devices. A field effect device structure comprising a semiconductor p-n junction adjacent to an insulated gate electrode is utilized in which a depletion region is created under the gate electrode in the presence of alternating forward and reverse biasing of the p-n junction. During the forward bias condition minority carriers are injected into the semiconductor substrate adjacent to the gate electrode structure.

Abstract: A memory input signal dynamic logic buffer circuit for providing FET level complementary output signals in response to low level input signals. The circuit is compatible with a variety of bipolar transistor driving logic families as the input signal sensitivity may set external to the circuit. The circuit includes a cross-coupled dynamic latch responsive to gated input and reference signals. Voltage boosting capacitors coupled to the latch nodes provide for simultaneous setting of the latch and boosting of the output nodes, which are connected to dynamic output driver circuits.

Abstract: The disclosure teaches the use of aluminum nitride as a mask for utilization of ion implantation in the formation of semiconductor configurations as well as an underlying material for use in semiconductor lift-off techniques in device formation and the deposition of metallization contact lines and interconnections.

Abstract: A differential sense amplifier for semiconductor memory cells is described which uses charge transfer preamplification in combination with a ratioless cross-coupled latch circuit to provide sensing and regeneration of binary information stored in a charge storage device. The sense amplifier may be utilized in arrays of single FET/capacitor memory cells in which the sense amplifier is centrally located and data input/output connections are made at one outside edge of the array. Single bit line driving is made possible by the use of a bit decoder which unconditionally couples charge to a single bit line common mode charge coupling to decrease potentials on a pair of bit lines coupled to the sense amplifier. The common mode bit line discharge means also increases response of the charge transfer preamplifier stage. A single transmission gate device is used for both reading out from a single bit line and writing new data into a memory cell, thus simplifying the input/output circuitry.

Abstract: A high speed ratioless FET sense amplifier for sensing stored information in a semiconductor memory system. The amplifier is capable of sensing very small voltage signals provided by charges stored in a plurality of single FET/capacitor memory cells. The amplifier comprises a pair of cross-coupled FET devices coupled to a pair of bit/sense lines by clock signal responsive switching devices. The source electrodes of the cross-coupled FETs are each independently capacitively coupled to another clock signal and also to a source of low potential through a pair of clock driven source pull-down FETs. The amplifier uses minimal size devices and is process parameter independent.

Abstract: An integrated circuit memory system includes capacitive storage memory cells capable of storing n bits of information on n capacitors associated with multiple emitters of a bilaterally conductive bipolar transistor. Each capacitor is coupled to a separate bit/sense line. Access of a storage cell is achieved by forward biasing the common base/collector junction of the bipolar transistor. Writing is achieved by driving the bit/sense lines to charge or discharge the storage capacitors during an access cycle. In reading, or sensing, the charged state of each storage capacitor is determined by sensing potential changes on the bit/sense lines during access. Fabrication of memory arrays is possible by any one of several different techniques, all of which are compatible with high speed bipolar logic circuits.

Abstract: Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.