Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.

Abstract: A memory array comprising a number of memory cells, a set path, a signal path, and at least one word line for transmitting a word line select signal to a row of the memory cells. The word line extends from a first driver end to a second end. The memory array further includes a dummy word line extending from the first driver end to a point between the first and second ends and back to the first end for transmitting a tracking signal responsive to the word line select signal. By folding the dummy word line in this manner, improved tracking of the set path with the signal path is achieved.

Abstract: An apparatus for and method of conditioning a polishing pad suitable for in-situ use, is described. The apparatus consists of a wedge-shaped conditioning plate whose width varies as a function of its length and whose exact geometry is a function of the radial effects of the polishing process effecting conditioning of the polishing pad. The conditioning plate rests on the polishing pad and is surrounded by a loose-fitting frame that holds the conditioning plate stationary with respect to the rotating polishing table, preventing lateral movement of the conditioning plate, but allowing the plate to move in the vertical direction so that it can rest flat on the polishing pad.

Abstract: The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin continuous layer to titanium--titanium nitride and a thick layer of a refractory metal, e.g. tungsten, overlying the titanium nitride layer.

Abstract: An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. A first plurality of memory cells coupled to the master word lines stores access information corresponding to a plurality of data words stored in a second plurality a memory cells coupled to a plurality of local word lines. The cache stores tag, index and Least Recently Used (LRU) information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data.

Abstract: A truc/complement receiver driver circuit in which the input signals may be applied prior to a sysnchronous clock signal. The input signals are sensed and latched to generate complementary output signals. The generation of the output signals causes the receiver portion of the circuit to be automatically reset for the next cycle. The leading edge of the systemclock causes the circuit outputs to reset and enables the receiver circuit to be enabled for the next cycle. Multiplexed input receiver circuits allow the circuit to respond to a plurality of input signal sources.

Abstract: The high speed greater than or equal to compare circuit comprises an equal to compare circuit having M number of exclusive-OR gates input into a NOR gate, each exclusive-OR gate N of the M number of exclusive-OR gates receiving as inputs a Nth bit of a first digital number having M bits and a corresponding Nth bit of a second digital number having M bits, wherein 1<N<M. Each exclusive-OR gate outputs a Nth not-equal signal indicating when the Nth bit of the first digital number is not equal to the corresponding Nth bit of the second digital number, whereby the output signal of the NOR gate indicates that the first digital number is equal to the second digital number.

Abstract: A virtual triple ported cache operates as a true triple ported array by using a pipelined array design. Multiple execution units can access the cache during the same cycle that the cache is updated from a main memory. The pipelined features of the cache allow for three separate sequential operations to occur within a single cycle, and thus give the appearance of a virtual triple ported array. This virtual triple port array architecture contains a data interface for dual execution units, which allows both units to access the same data array location. The array architecture allows for back-to-back read accesses occurring within a half cycle. The array architecture provides a bypassing function around the array for a write occurring on one port to the same address that a read is occurring on the other port. To allow for simultaneous cache reloads during execution unit access, a late write is done at the end of the cycle.

Abstract: A high density substrate plate trench DRAM cell memory device and process are described in which a buried region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is contacted along its perimeter by a reach through region to complete the isolation. The combined regions reduce charge loss due to better control of device parasitics.

Abstract: A fuse download system for programming decoders for redundancy. Auxiliary fuse banks have sets of fuses that store logic states that (a) select a redundant decoder and (b) indicate the address of a faulty row/column of memory cells. When the chip is first powered up, each set of fuses is accessed and downloaded to program selected redundant decoders. Because the fuse sets can be dynamically assigned to redundant decoders on an any-for-any basis, the fault tolerance of the redundancy system is enhanced.

Abstract: A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.

Abstract: A high density substrate plate trench DRAM cell memory device and process are described in which a buried region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is contacted along its perimeter by a reach through region to complete the isolation. The combined regions reduce charge loss due to better control of device parasitics.

Abstract: A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches.

Abstract: A memory system with adaptable redundancy comprises address decoding means (200) for the selection of one of the rows R.sub.1 to R.sub.2 (n+1) in the memory array, according to the binary value of address A.sub.0, A.sub.1, . . . A.sub.nn incoming on bus 102. Block 200 comprises 2.sup.(n+1) blocks 201 being able to drive an activation signal on leads R.sub.1 to R.sub.2 (n+1), and having an output connected to a lead 206.Block 205 is able to drive an activation signal on lead RR according to signals present on leads 107 and 206, so as to select redundant row RR.sub.1 without the use of a redundant address decoder.

Abstract: A high density substrate plate DRAM cell memory device and process are described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by lateral outdiffusion from the sidewalls of the deep trenches and partially formed by an N-well surface diffusion which entirely surrounds the DRAM array region.

Abstract: A high density substrate plate DRAM cell memory device is described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by lateral outdiffusion from the sidewalls of the deep trenches and partially formed by an N-well surface diffusion which entirely surrounds the DRAM array region.

Abstract: A method is provided to enable the formation of sub-lithographic relief images to increase the surface area of semiconductor structures for use in the storage nodes of DRAM cells. The method includes the steps of forming in situ a non-planar region having a relief pattern comprising sub-micron sized elements and the transferring the relief pattern into a masking layer in order to selectively etch a substrate to form relatively deep trenches having a density equal to the relief pattern. Polysilicon and porous silicon can be used to form the sub-micron relief pattern.

Abstract: A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches.

Abstract: A process is described which eliminates the need to account for mask alignment tolerances in forming vias for metallurgy by the use of a common vertical edge or common plane defined by a first mask representing a first level of interconnect. Subsequent masks for defining interconnecting vias and a second level of interconnect utilize at least one edge of the first mask pattern as a common element to define subsequent metal levels. The combination of an etch stop layer and an oversized second level mask enable the mask overlay to be eliminated.

Abstract: Three-dimensional semiconductor structures are taught in which various device types are formed from a plurality of planar layers on a substrate. The major process steps include the formation of a plurality of alternating layers of material, including semiconductor and dielectric materials, forming a vertical access hole in the layers, processing the layers selectively to form active or passive semiconductor devices, and filling the access hole with a conductor. The ultimate structure includes a three-dimensional memory array in which entire dynamic memory cells are fabricated in a stacked vertical orientation above support circuitry formed on a planar surface.