Abstract: A multi-chip package according to an aspect of this disclosure includes a plurality of multi-chips. Each of the multi-chips includes a lead configured to receive an external power supply voltage, and a pad circuit configured to reset an internal node to the level of a ground voltage and to generate chip address information by controlling the potential of the internal node based on the state of a connection between the pad circuit and the lead.
Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.
Abstract: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.
Abstract: A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers.
Abstract: A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.
Abstract: A semiconductor memory device includes a memory string coupled between a common source line and a bit line, a page buffer configured to supply a first precharge voltage to the bit line and to latch data corresponding to a threshold voltage level of a memory cell of the memory string, wherein the data is detected according to a shift in a voltage of the bit line, in a precharge operation, a precharge circuit configured to supply a second precharge voltage to the common source line in the precharge operation, and a voltage supply circuit configured to generate operating voltages for turning on the memory string in the precharge operation. While the first precharge voltage is supplied from the page buffer to the bit line, the second precharge voltage is supplied to the bit line through the memory string.
Abstract: A semiconductor memory device comprises planes each configured to comprise flag cells storing data about program methods of memory cells of the plane, page buffer units configured to sense the data of the flag cells, a flag cell data detection circuit configured to make a determination of program methods of the planes on the basis of a result, obtained by comparing the sensed data of the flag cells of the planes, and the sensed data of the flag cells, and a microcontroller configured to control the page buffer units, wherein the page buffer units read least significant bit (LSB) data of the planes or both the least significant bit (LSB) data and most significant bit (MSB) data on the basis of the determination of the flag cell data detection circuit.
Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.
Abstract: A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels.
Abstract: A nonvolatile memory device comprises a memory cell array including a number of bit lines commonly coupled to a source line and each coupled to a number of memory cells, a delay unit configured to delay a sense signal in response to a voltage level of the source line and to output a delayed sense signal, and a page buffer unit configured to sense voltage levels of the bit lines in response to the delayed sense signal.
Abstract: A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.
Abstract: A semiconductor device includes: a first reference voltage generator for generating a first reference voltage; a first band gap circuit for dividing a voltage at a second reference voltage output node to produce a first and a second band gap voltages having a property relative to temperature variations; a first comparator for receiving the first reference voltage as a bias input and comparing the first band gap voltage with the second band gap voltage; and a first driver for pull-up driving the second reference voltage output node in response to an output signal of the first comparator.
Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
Abstract: A magneto-resistance element is provided. The magneto-resistance element includes an underlying layer including a main metal selected from electrically conductive metals and an auxiliary metal selected from transition metals, a first magnetic layer stacked on the underlying layer, an insulation layer stacked on the first magnetic layer, and a second magnetic layer stacked on the insulation layer.
Abstract: An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code modification unit configured to generate a modified impedance code by performing an operation on the first impedance code according to a setting value, and a second code generation unit configured to generate a second impedance code based on the modified impedance code.
Abstract: A method for fabricating a vertical channel type non-volatile memory device including a plurality of memory cells stacked along channels protruding from a substrate includes: alternately forming a plurality of first material layers and a plurality of second material layers over the substrate; forming a buffer layer over the substrate with the plurality of the first material layers and the plurality of the second material layers formed thereon; forming trenches by etching the buffer layer, the plurality of the second material layers, and the plurality of the first material layers; forming a material layer for channels over the substrate to fill the trenches; and forming the channels by performing a planarization process until a surface of the buffer layer is exposed.
Abstract: A resistive memory device includes: a bottom electrode formed over a substrate; and an insulation layer having a hole structure formed over the substrate structure. Herein, the hole structure exposes the bottom electrode, has sidewalls of positive slope, and has a bottom width equal to or smaller than a width of the bottom electrode; a resistive layer formed over the hole structure; and an upper electrode formed over the resistive layer.
Abstract: In a semiconductor memory device which performs a repair method of replacing a repair target word line and one adjacent word line at the same time by a repair operation through an efficient decoding operation for selecting a repair target address, a test operation of enabling only a word line corresponding to a cell coupled to a bit line or a bit line bar is stably performed.
Abstract: A method for fabricating a semiconductor device includes forming an isolation layer which defines an active region in a substrate, forming recess patterns in the active region and the isolation layer, baking a surface of the recess pattern by conducting an annealing process and forming a gate dielectric layer over a surface of the recess pattern by conducting an oxidation process.
Abstract: An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.