Abstract: Provided is a method for forming a buried word line in a semiconductor device. The method includes forming a trench by etching a pad layer and a substrate, forming a conductive layer to fill the trench, planarizing the conductive layer until the pad layer is exposed, performing an etch-back process on the planarized conductive layer, and performing an annealing process in an atmosphere of a nitride-based gas after at least one of the forming of the conductive layer, the planarizing of the conductive layer, and the performing of the etch-back process on the planarized conductive layer.

Abstract: A package apparatus includes at least one memory chip, a voltage detection circuit configured to make a determination of whether a voltage supplied to the memory chip is a specific voltage or higher, and a controller configured to control an operation of the memory chip based on a result of the determination.

Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.

Abstract: A fuse layout structure of a semiconductor device includes a plurality of fuses in a fuse open area, wherein three neighboring fuses of the plurality of fuses form a fuse unit, and at least one of the fuses partially overlaps at least one of the other fuses of the same fuse unit in the fuse open area.

Abstract: A nonvolatile memory device includes a data latch unit configured to store data to be programmed into a memory cell or store data read from a memory cell, and page buffers each comprising a sense node discharge unit configured to selectively ground a sense node depending on data stored in the data latch unit and in response to a sense node discharge signal.

Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

Abstract: An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

Abstract: A data transfer circuit has a reduced number of lines for transferring a training pattern used in a read training for high speed operation, by removing a register for temporarily storing the training pattern, and a semiconductor memory device including the data transfer circuit. The data transfer circuit includes a latch unit and a buffer unit. The latch unit latches one bit of a training pattern data input together with a training pattern load command whenever the training pattern load command is input. The buffer unit loads a plurality of bits latched in the latch unit, including the one bit of training pattern data, in response to a strobe signal.

Abstract: A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.

Abstract: A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.

Abstract: A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.

Abstract: A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.

Abstract: A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.

Abstract: A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal and output a generated programming voltage to the core region.

Abstract: An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a test operation is activated.

Abstract: A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching.

Abstract: A method of operating a nonvolatile memory device includes precharging bit lines coupled to strings, supplying a first verification voltage to a selected word line and supplying a pass voltage to word lines other than the selected word line, supplying a first sense pulse to switching elements coupled between the bit lines and sense nodes and detecting memory cells, each having a threshold voltage higher than the first verification voltage, supplying a second verification voltage higher than the first verification voltage to the selected word line and supplying the pass voltage to the word lines other than the selected word line, and supplying a second sense pulse to the switching elements and detecting memory cells, each having a threshold voltage higher than the second verification voltage.