Patents Represented by Attorney IP & T Group LLP
  • Patent number: 8310882
    Abstract: A package apparatus includes at least one memory chip, a voltage detection circuit configured to make a determination of whether a voltage supplied to the memory chip is a specific voltage or higher, and a controller configured to control an operation of the memory chip based on a result of the determination.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Kyu Lee
  • Patent number: 8310062
    Abstract: A semiconductor package includes a wire board, a plurality of semiconductor chips configured to be stacked over the wire board and to be electrically coupled with the wire board, and at least one shielding unit configured to be formed between the plurality of semiconductor chips and to be maintained at a predetermined voltage.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun-Ho Lee, Hyung-Dong Lee, Hyun-Seok Kim
  • Patent number: 8309416
    Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Shil Park, Yong-Seok Eun, Kee-Jeung Lee, Min-Soo Kim
  • Patent number: 8305838
    Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mun-Phil Park
  • Patent number: 8305819
    Abstract: A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwang-Hyun Kim, Kang-Youl Lee
  • Patent number: 8305837
    Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mun-Phil Park
  • Patent number: 8304853
    Abstract: A fuse layout structure of a semiconductor device includes a plurality of fuses in a fuse open area, wherein three neighboring fuses of the plurality of fuses form a fuse unit, and at least one of the fuses partially overlaps at least one of the other fuses of the same fuse unit in the fuse open area.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong-Ho Kim
  • Patent number: 8305108
    Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byung-Deuk Jeon, Dong-Geum Kang, Young-Jun Yoon
  • Patent number: 8305813
    Abstract: A nonvolatile memory device includes a data latch unit configured to store data to be programmed into a memory cell or store data read from a memory cell, and page buffers each comprising a sense node discharge unit configured to selectively ground a sense node depending on data stored in the data latch unit and in response to a sense node discharge signal.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Kyu Lee
  • Patent number: 8300481
    Abstract: A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: October 30, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang-Ho Do, Jae-Il Kim
  • Patent number: 8300482
    Abstract: A data transfer circuit has a reduced number of lines for transferring a training pattern used in a read training for high speed operation, by removing a register for temporarily storing the training pattern, and a semiconductor memory device including the data transfer circuit. The data transfer circuit includes a latch unit and a buffer unit. The latch unit latches one bit of a training pattern data input together with a training pattern load command whenever the training pattern load command is input. The buffer unit loads a plurality of bits latched in the latch unit, including the one bit of training pattern data, in response to a strobe signal.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: October 30, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ji-Hyae Bae
  • Patent number: 8299846
    Abstract: An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: October 30, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Patent number: 8296610
    Abstract: A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: October 23, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji-Eun Jang, Seok-Cheol Yoon
  • Patent number: 8295100
    Abstract: A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: October 23, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeng-Ouk Lee
  • Patent number: 8295121
    Abstract: A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: October 23, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwan Dong Kim
  • Patent number: 8289787
    Abstract: A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal and output a generated programming voltage to the core region.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji-Hwan Kim, Seong-Je Park
  • Patent number: 8288263
    Abstract: A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Gyu-Hyun Kim, Kwon Hong, Cha-Deok Dong
  • Patent number: 8289794
    Abstract: An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a test operation is activated.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Joo Ha
  • Patent number: 8289761
    Abstract: A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Chan Park, Gap-Sok Do, Jang-Uk Lee
  • Patent number: 8283609
    Abstract: An on die thermal sensor in a semiconductor memory device includes: a reference voltage generating unit for generating a band gap voltage and generating a reference voltage by using the base band gap voltage; a voltage amplifying unit for outputting a temperature voltage by amplifying the band gap voltage; and a temperature information code generating unit for generating a temperature information code corresponding to a voltage level of the temperature voltage, wherein voltage variation of the temperature voltage is amplified as much as a preset amplifying value and a maximum voltage level of the temperature voltage is maintained lower than that of a power supply voltage used in the semiconductor memory device.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 9, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chun-Seok Jeong