Patents Represented by Attorney IP & T Group LLP

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  • Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same
    Patent number: 8050136
    Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mun-Phil Park
  • Apparatus for generating a voltage and non-volatile memory device having the same
    Patent number: 8050099
    Abstract: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: In Soo Wang, Yu Jong Noh, Lee Hyun Kwon, Bon Kwang Koo
  • Parallel-to-serial conversion circuit and method thereof
    Patent number: 8049649
    Abstract: A parallel-to-serial conversion circuit for converting pieces of parallel data into serial data, and a parallel-to-serial converting method thereof include: a shifter configured to sequentially shift an initiation signal to generate a plurality of transfer activation signals; a valid duration generator configured to define valid durations of the plurality of pieces of parallel data based on a clock and the plurality of transfer activation signals; and an output unit configured to receive the plurality of pieces of parallel data whose valid duration has been defined and to drive an output in response to a piece of data from among the received parallel data whose valid duration has begun.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jinyeong Moon
  • Data output timing in response to read command based on whether delay locked loop is enabled/disabled in a semiconductor device
    Patent number: 8050119
    Abstract: A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Chon Park
  • Semiconductor memory device
    Patent number: 8050118
    Abstract: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Whan Kim, Seok-Cheol Yoon
  • Transistor including bulb-type recess channel and method for fabricating the same
    Patent number: 8048742
    Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Hong-Seon Yang, Dong-Sun Sheen, Se-Aug Jang, Heung-Jae Cho, Yong-Soo Kim, Min-Gyu Sung, Tae-Yoon Kim
  • Programming method of non-volatile memory device
    Patent number: 8050088
    Abstract: A programming method of a non-volatile memory device having a drain select transistor, a source select transistor, and a plurality of memory cells connected between the drain select transistor and the source select transistor includes applying a program voltage, which increases stepwise according to a repetition of a program cycle, to a selected memory cell and applying a pass voltage, which decreases in inverse proportion to change of the program voltage, to some of unselected memory cells.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won-Hee Lee
  • Integrated circuit
    Patent number: 8049554
    Abstract: An integrated circuit includes a first internal voltage generating unit configured to receive an external power and to generate a first internal voltage, and a second internal voltage generating unit configured to receive the first internal voltage, and to generate a second internal voltage having an absolute value of a target voltage level that is less than an absolute value of the first internal voltage, wherein the second internal voltage generating unit is initially enabled at a later time than the first internal voltage generating unit is initially enabled.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Hwan Kim
  • Semiconductor memory device
    Patent number: 8050127
    Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joong-Ho Lee
  • Semiconductor device
    Patent number: 8050310
    Abstract: A semiconductor device includes a transmitting unit for receiving plural bits of data to modulate the data to a 1-bit pulse signal whose pulse width corresponds to a value of the data and transferring the pulse signal to a transfer line; and a receiving unit for receiving the pulse signal transferred through the transfer line to demodulate the pulse signal to the plural bits of data.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Joo Ha
  • Memory device having latch for charging or discharging data input/output line
    Patent number: 8050110
    Abstract: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Jin Byeon, Beom-Ju Shin
  • Method of programming nonvolatile memory device
    Patent number: 8050097
    Abstract: According to an aspect of a method of programming a nonvolatile memory device, a first program operation command is input, and a program operation is executed according to a program start voltage stored in a program start voltage storage unit. Here, a program voltage, which is applied at a time point at which a memory cell programmed higher than a verify voltage while the program operation is performed occurs for the first time, is updated to a program start voltage.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Hyun Wang
  • Word line driver, method for driving the word line driver, and semiconductor memory device having the word line driver
    Patent number: 8050133
    Abstract: A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driving signal, wherein the word line is driven concurrently with an activation of the main word line driving signal. The word line driver can reduce the unnecessary current consumption.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae-Sik Yun, Kang-Seol Lee
  • Semiconductor memory device capable of controlling tAC timing and method for operating the same
    Patent number: 8050374
    Abstract: A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The delay locked loop circuit produces delay locked clock signals through a delay locking operation. The tAC control unit adjusts a delay value of the delay locked clock signals in order to control a tAC timing, thereby generating output reference signals. The reference signal generating unit produces a latch reference signal in response to the delay locked clock signals. The data output block latches data in response to the latch reference signal and for outputting the latched data in response to the output reference signals.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung-Nam Kim, Ho-Youb Cho
  • Delay locked loop circuit
    Patent number: 8049544
    Abstract: A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nam-Pyo Hong, Jin-Youp Cha
  • Dielectric structure in nonvolatile memory device and method for fabricating the same
    Patent number: 8049268
    Abstract: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwon Hong, Kwan-Yong Lim
  • Fuse apparatus for controlling built-in self stress and control method thereof
    Patent number: 8050122
    Abstract: A fuse apparatus for controlling a built-in self stress unit includes a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end signal when one cycle for the generated stress test pattern has ended, and a fuse configured to record an operation state of the built-in self stress according to the one-cycle end signal. A method for controlling a built-in self stress includes repeatedly generating any stress test mode, in a test mode counting the generated stress test pattern, and activating a cycle end signal when a counting value reaches a predetermined value, and recording an operation state of the built-in self stress in a fuse on the basis of the counted value.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Il Chung
  • Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device
    Patent number: 8045394
    Abstract: A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Semiconductor memory device and method for driving the same
    Patent number: 8046663
    Abstract: A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyuck-Soo Yoon
  • On-die termination control circuit of semiconductor memory device
    Patent number: 8044679
    Abstract: On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transfer the first code and the second code in response to a first termination command and a normal termination controller configured to compare the first code and the second code with each other to determine enabling/disabling timings of a termination operation in response to a second termination command.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung-Whan Kim