Patents Represented by Attorney IP & T Group LLP

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  • Groundwater radon reduction apparatus
    Patent number: 8070944
    Abstract: A groundwater radon reduction apparatus is provided. The groundwater radon reduction apparatus includes: a housing in which groundwater falls down; a rotating member installed in the housing and rotated by a falling force of the groundwater to form the groundwater into water drops; a plurality of power transmission members connected to both ends of the rotating member to transmit power, and receiving the rotating force of the rotating member; and a plurality of ventilation units coupled to one ends of the power transmission members inside the housing, respectively, and rotated together with the power transmission members by the rotation force of the rotating member to discharge radon gases within the water drops to the outside.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: December 6, 2011
    Assignee: Korea Institute of Geoscience and Mineral Resources
    Inventors: Kil Yong Lee, Yoon Yeol Yoon, Kyung Seok Ko
  • Delay cell and phase locked loop using the same
    Patent number: 8072254
    Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon
  • Integrated circuit
    Patent number: 8067969
    Abstract: An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 29, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo-Hyun Seo
  • Semiconductor memory device
    Patent number: 8068372
    Abstract: A semiconductor memory device includes: a repair node; a fuse one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse; and a voltage drop unit coupled between the pull-up unit and the fuse and configured to lower a voltage level of the driving voltage.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: November 29, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae-Sig Chang
  • Method of fabricating transistor for semiconductor device
    Patent number: 8062948
    Abstract: A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: November 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min-Jung Shin
  • Semiconductor memory apparatus and a method for reading data stored therein
    Patent number: 8064283
    Abstract: A semiconductor memory apparatus includes a data bus inversion (DBI) section configured to receive a plurality of input data and decide whether to invert or output, without an inversion, the plurality of input data depending upon logic levels of the plurality of data, and further configured to generate a plurality of inversion data based on the decision; and a data output section configured to receive the plurality of inversion data, invert or output, without an inversion the plurality of inversion data in response to a mode signal, and generate a plurality of output data.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: November 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Wook Kwak, Kwan Weon Kim
  • Phase locked loop and method for operating the same
    Patent number: 8063677
    Abstract: A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwan-Dong Kim
  • Method of programming nonvolatile memory device
    Patent number: 8059460
    Abstract: A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: November 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byoung Kwan Jeong, Chul Woo Yang, Mi Sun Yoon
  • Semiconductor memory device
    Patent number: 8059480
    Abstract: A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: November 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Yeon Lee, Young-Hoon Oh
  • Power up signal generation circuit and method for generating power up signal
    Patent number: 8054113
    Abstract: A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Method of programming nonvolatile memory device
    Patent number: 8054685
    Abstract: A method of sequentially performing a LSB program operation and an MSB program operation of a nonvolatile memory device, wherein the nonvolatile memory device comprises multi-level memory cells each configured to store two pieces of bit information and page buffers each coupled to a bit line coupled with the memory cells and configured to comprise a first latch coupled to first and second nodes and a second latch coupled to third and fourth nodes, the method including inputting data of MSBs to the second and fourth nodes and setting data of the second and fourth nodes according to a state of data of LSBs stored in the memory cells, and precharging the bit line according to a combination of data stored in the first and second latches and performing the MSB program operation according to a state of a LSB program operation stored in the memory cells.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Oh Lim
  • Semiconductor memory device having a redundancy memory cell array
    Patent number: 8054704
    Abstract: A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Myung Kyung
  • Semiconductor memory device with signal aligning circuit
    Patent number: 8054702
    Abstract: A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hwang Hur, Chang-Ho Do
  • Method for fabricating semiconductor device
    Patent number: 8053341
    Abstract: A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Baek-Mann Kim
  • OP-amp circuit
    Patent number: 8054132
    Abstract: An OP-amp circuit includes a first circuit unit configured to generate an operating voltage in response to an enable signal, a second circuit unit configured to amplify a difference between respective voltages received through an inverting terminal and a non-inverting terminal in response to the operating voltage and to output a result of the amplification as a first drive voltage, a third circuit unit configured to output a second drive voltage according to a voltage level of the first drive voltage inputted thereto, and a fourth circuit unit configured to divide an input voltage inputted thereto into a divided voltage according to two resistances having respective resistive values varying according to the first and second drive voltages and to output the divided voltage through an output terminal.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yu Jong Noh
  • Delay locked loop and semiconductor memory device with the same
    Patent number: 8054701
    Abstract: A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking control unit. The delay-locked clock signal generating unit performs a delay locking operation on a clock signal, thereby generating a delay-locked clock signal. The mode signal generating unit enables a fast precharge power-down mode signal in a fast precharge power-down mode. The delay locking control unit controls the delay-locked clock signal generating unit to be activated in a predetermined cycle in response to the fast precharge power-down mode signal.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Jun Ku
  • Method of programming nonvolatile memory device
    Patent number: 8050103
    Abstract: In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this determination, to-be-programmed data are input based on information about the number of set data bits, and programming and verification are performed.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: You Sung Kim, Byung Ryul Kim
  • Method for fabricating vertical channel type nonvolatile memory device
    Patent number: 8048743
    Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Hong Lee, Moon-Sig Joo, Kwon Hong, Sun-Hwan Hwang
  • Program method of nonvolatile memory device
    Patent number: 8050098
    Abstract: A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell block. Electric charges charged to a channel of memory cell strings included in unselected memory cell blocks are discharged. A verify operation is performed on the selected memory cell block.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong Je Park
  • Internal voltage generator of semiconductor device
    Patent number: 8049552
    Abstract: An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Jin Byeon