Patents Represented by Attorney IP & T Group LLP

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  • Double-tube type stent
    Patent number: 8043355
    Abstract: A double-tube type stent is inserted into a hollow tubular organ such as a bile duct so as to relieve narrowing of the bile duct on, for instance, an anastomotic area of the intrahepatic bile duct of a liver transplant patient. A hollow cylindrical body has a plurality of rhombic spaces formed by weaving a superelastic shape-memory-alloy wire so as to be crossed. A silicon coating layer is coated on an outer surface of the cylindrical body using a silicon solution. A polytetrafluoroethylene (PTFE) tube is fixedly fitted around the cylindrical body having the silicon coating layer leaving a gap therebetween.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: October 25, 2011
    Assignees: Taewoong Medical Co., Ltd.
    Inventors: Kyong-Min Shin, Jeung-Hee Nam
  • Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh
    Patent number: 8045411
    Abstract: A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Hoon Kim, Patrick B. Moran
  • Data output circuit in a semiconductor memory apparatus
    Patent number: 8045399
    Abstract: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Yeol Yang
  • Semiconductor memory device having common circuitry for controlling address and data mask information
    Patent number: 8045397
    Abstract: A semiconductor memory device is capable of controlling an address and data mask information through the use of a common part, thereby reducing chip size. The semiconductor memory device for receiving the addresses and data mask information via a common pin includes a buffer unit and a shift register unit. The buffer unit receives the addresses and data mask information. The shift register unit is comprised of a plurality of latch stages connected in series, for sequentially latching the addresses and data mask information being inputted in series, and an address output unit and a data mask information output unit for outputting information from different latch stages.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Chang Kwean
  • On die thermal sensor of semiconductor memory device
    Patent number: 8042999
    Abstract: An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chun-Seok Jeong, Yong-Ki Kim
  • Phase-change memory device
    Patent number: 8045368
    Abstract: A phase-change memory device performs a buffer program operation in response to a buffer program command sequence. The phase-change memory device includes a page buffer unit configured to store a plurality of input data corresponding to a word count value of a buffer program command sequence and selectively output the stored input data in response to a selection signal, and a page buffer control unit configured to generate the selection signal determined by counting a value representing the word count value.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ho-Seok Em
  • Circuit and method for controlling read cycle
    Patent number: 8045400
    Abstract: A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Je-Yoon Kim, Jong-Chern Lee
  • Program method of nonvolatile memory device
    Patent number: 8045393
    Abstract: According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byung Ryul Kim, Jun Seop Chung, Duck Ju Kim
  • Internal voltage generating circuit of semiconductor device
    Patent number: 8040177
    Abstract: An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: October 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Delay locked loop circuit
    Patent number: 8040169
    Abstract: A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin-Il Chung, Hoon Choi
  • Electrostatic discharge protection device
    Patent number: 8039899
    Abstract: An electrostatic discharge protection device includes a first well comprising a MOS transistor; a second well comprising a first impurity region to which a first voltage is applied, and a second impurity region connected to an input/output pad, the second well being disposed adjacent to the first well; and a third well comprising a third impurity region to which the first voltage is applied, the third well being disposed adjacent to the second well.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: October 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Ju Lim
  • Data output circuit and method
    Patent number: 8036046
    Abstract: A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same number of bits as that of the first parallel data signals in response to the first strobe signal and the first delayed strobe signal, a storing block configured to latch the second parallel data signals in response to a second strobe signal and a second delayed strobe signal, and a parallel-to-serial converting block configured to sequentially output the second parallel data signals latched in the storing block, wherein the first strobe signal is used to generate a data signal that is outputted first among the second parallel data signals.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kang-Youl Lee
  • Semiconductor device and method for operating the same
    Patent number: 8035420
    Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Yeon Byeon
  • Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line
    Patent number: 8036053
    Abstract: Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jeong-Yoon Ahn, Ji-Eun Jang, Young-Jun Ku
  • Output driver
    Patent number: 8035418
    Abstract: An output driver of a semiconductor device includes driving transistors and a body bias providing unit. The driving transistors are coupled in parallel and configured to drive an output terminal. The body bias providing unit is configured to supply the driving transistors with respective body biases of at least two levels.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ic-Su Oh, Hyung-Soo Kim, Chang-Kun Park
  • Electrostatic discharge circuit
    Patent number: 8035937
    Abstract: An electrostatic discharge device has relatively superior characteristics for protecting a gate insulation layer of an input buffer transistor of a semiconductor device from static electricity while minimizing signal delay. The electrostatic discharge circuit includes a main electrostatic discharge section configured to discharge static electricity inputted to an input/output pad to at least one voltage line, an input impedance section configured to adjust an amount of current flowing from the input/output pad depending upon a frequency of an input signal of the input/output pad, an auxiliary electrostatic discharge section connected to the input impedance section and configured to discharge the static electricity inputted to the input/output pad to the at least one voltage line, and an input buffer connected between the auxiliary electrostatic discharge section and an internal circuit.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kook-Whee Kwak
  • High voltage generator and word line driving high voltage generator of memory device
    Patent number: 8035441
    Abstract: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Il Kim, Chang-Ho Do
  • Semiconductor device and driving method thereof
    Patent number: 8035429
    Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae-Kyun Kim
  • Power-up circuit for semiconductor memory device
    Patent number: 8035428
    Abstract: A power-up circuit for a semiconductor memory device includes a voltage division unit configured to divide a power supply voltage, a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal and a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Khil-Ohk Kang
  • Semiconductor device and semiconductor package including the same
    Patent number: 8035194
    Abstract: Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun-Ho Lee, Hyung-Dong Lee, Hyun-Seok Kim