Abstract: A parallel to serial conversion circuit makes output data normally swing even in a high-speed operation. The parallel to serial conversion circuit includes a main selection block configured to drive an output node sequentially in response to data on a first line and data on a second line, and a subsequent selection block configured to drive the output node sequentially in response to data on a subsequent first line and data on a subsequent second line, wherein the output node is driven by inverted data of the data on the subsequent first line and inverted data of the data on the subsequent second line.

Abstract: A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

Abstract: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are read as having a threshold voltage lower than the first read voltage, when the number is a critical value or more, resetting a read voltage, and performing, based on the reset read voltage, a read operation on memory cells that belong to the same memory cell block as the dummy cells and on which a program operation has been performed on the memory cells after the nth erase operation has been performed.

Abstract: A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.

Abstract: A power distributor includes a large reservoir capacitor, a switch coupled between at least one power supply line and the large reservoir capacitor, and a controller configured to turn on or off the switch based on whether a circuit block connected to the power supply line is in operation or not.

Abstract: A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.

Abstract: A data output device of a semiconductor memory apparatus includes detection means configured to detect a specified operation frequency range; pre-driving means configured to be inputted with signals; driving means configured to receive outputs of the pre-driving means and drive an output of data; and adjustment means configured to adjust a slew rate of the driving means under the control of an output signal of the detection means.

Abstract: Provided is a technology for monitoring the electrical resistance of an element such as a fuse whose resistance is changed due to the electrical stress among internal circuits included in a semiconductor device. The present invention provides a monitoring circuit to monitor the change in the device specification during the device is being programmed and after the device is programmed. The present invention enables the verification of an optimized condition to let the device have a certain electrical resistance, by comparing the load voltage and the fuse voltage with the reference voltage that can sense the range of resistance variation more precisely. Also, it can guarantee device reliability since it is still possible to sense electrical resistance after the electrical stress is being given. Also, the present invention can increase the utility of the fuse by possessing an output to monitor electrical resistance sensed inside of the semiconductor.

Abstract: A high voltage generation circuit includes a clock logic unit configured to generate a switch clock signal and a pump clock signal, that has a varying frequency, in response to an input signal, a high voltage unit configured to generate a high voltage in response to the pump clock signal, a high voltage switch configured to output a selection signal in response to the switch clock signal, and a switching element configured to transfer the high voltage, generated by the high voltage unit, to an output node in response to the selection signal.

Abstract: A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.

Abstract: A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or more repair word lines arranged in each of the cell arrays, and a plurality of repair information storages configured to store bank information and row addresses of the array word lines to be replaced with the repair word lines.

Abstract: A program and verify method of a nonvolatile memory device, which can minimize the time taken for program and verify operations. The program and verify method includes precharging an output terminal of a block selector to a second level, making the output terminal of the block selector float, and, in the state where the output terminal floats, sequentially applying a program voltage and a verify voltage through a global word line.

Abstract: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

Abstract: A method of inputting address in a nonvolatile memory device includes inputting a row address including an information for selecting a memory block and an information for selecting a page, and inputting a column including an information for selecting a column and an information for selecting a plane.

Abstract: A page buffer in a non-volatile memory device for performing a program operation for a multi level cell having m bits includes first register to mth registers, a first data transmitting circuit configured to transmit data stored in a first node or a second node of the first register to a sensing node in accordance with a first data transmitting signal or a second data transmitting signal, and (m?1) sensing node discharging circuits configured to couple the sensing node to ground in accordance with data stored in a first node or a second node of each of the second to mth registers, and a first sensing node discharge signal or a second sensing node discharge signal.

Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Abstract: A semiconductor memory device includes output enable signal generation means configured to be reset in response to an output enable reset signal, count a DLL clock signal and an external clock signal, and generate an output enable signal in correspondence to a read command and an operating frequency; and activation signal generation means configured to generate an activation signal for inactivating the output enable signal generation means during a write operation interval.

Abstract: A semiconductor memory device is capable of scrambling input/output data according to row addresses. The semiconductor memory device includes a local line driving block configured to differentially drive a positive local line and a negative local line by selectively inverting data on a global line according to row addresses, a global line driving block configured to drive the global line by selectively inverting data on the positive local line and data on the negative local line according to the row addresses, a first cell region configured to allow a first internal data to be equalized with the data on the positive local line in response to the row addresses and column addresses, and a second cell region configured to allow a second internal data to be equalized with the data on the negative local line in response to the row addresses and the column addresses.

Abstract: A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal, and a data write unit configured to output a program current in response to the write control signals and control a level of the program current according to a code combination of the write control codes.

Abstract: A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.