Abstract: The wiring design software 3 reads in design information, analyzes it to generate a wiring problem and correlates bonding pads and pins of a semiconductor package to each other (S102, S104). The wiring design software 3 then searches a wiring route while permitting crossing by using the Dijkstra method and the like, calculates an evaluation value by weighting the length of a candidate route with a coefficient W when the candidate route crosses a monitoring side E, and selects a candidate route having a minimum evaluation value as a partial route (S110).

Abstract: Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Qcrit and substantially eliminates soft errors due to alpha particles; susceptibility to which would otherwise increase as integrated circuits are scaled to smaller sizes and manufactured at increased integration densities. Formation of the added capacitance as deep trench capacitors avoids any constraint on circuit or memory cell layout. Degradation of performance is avoided and performance potentially improved by permitting alteration of proportions of pull-down and pass gate transistors in view of the increased stability imparted by the added capacitors. One of the capacitor electrodes is preferably shorted to the supply voltage through an impurity well. Thus, the memory cell size can be reduced while greatly reducing susceptibility to soft errors; contrary to the effects of scaling at current and foreseeable feature size regimes.

Abstract: A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the strap comprises a plurality of strap conductors and the strap has a lower resistance than the conductor. The conductor comprises a first material having a first resistance and the strap comprises a second material different than the first material having a second resistance, wherein the second resistance is lower than the first resistance. The plurality of strap conductors comprises at least two electrically connected strap conductors, and a first strap conductor is adjacent the conductor and a second strap conductor is adjacent the transistor and the first strap conductor has an improved interface with the conductor. The strap comprises a lip strap, wherein the strap forms an L-shape.

Abstract: A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.

Abstract: A multilayer thin film via landing pad structure includes a thin film conductor structure with a recessed landing pad formed between an upper layer of polyimide dielectric and a lower layer of polyimide dielectric. A multilayer thin film via landing pad structure is formed on a lower layer of dielectric having a top surface. A depression is formed in the top surface of the lower layer of dielectric. The depression has a bottom within the lower layer. A recessed landing pad comprising a conductor is formed in the depression on the surface of the lower layer of dielectric. A conductor line is formed on the lower layer of dielectric in contact with the recessed landing pad. An upper layer of dielectric is formed over the lower layer of dielectric, the thin film conductor line and the recessed landing pad. A conductive via is formed extending through the upper layer of dielectric into contact with the recessed landing pad.

Abstract: A method, system and structure for a pin grid or pad grid array structure includes a plurality of pins connected to an electronic structure, a power plane within the electronic structure electrically connected to power pins, a ground plane within the electronic structure, and fuse portions electrically connecting the ground plane to ground pins and signal pins. The power plane and the ground plane create a charge in the pins during electroplating of the pins. The fuse portions disconnecting the signal pins from the ground plane after the electroplating.

Abstract: A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.

Abstract: A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

Abstract: A venting lid cover for a container that has a plate member that configurably attaches to the coaming of the drum container, and a plenum member that attaches to this plate member. The plate member has at least one plate opening (preferably two for standard 55-gallon drums) that are equal in number to bung holes in the container so that the bung holes can pass through the plate member. The plenum member has vapor inlet ports that are equal in number and positioned in close proximity to the plate openings.

Abstract: A method to self-align a lithographic pattern to a workpiece, the method including the steps of obtaining a workpiece having a predetermined pattern of features; modifying at least some of the features so that when a photoresist material is applied to the pattern, there is a substantial difference in reflectivity between two adjacent features, at least one of which has been modified; applying a photoresist material; masklessly exposing the photoresist material; developing the photoresist material, the substantial difference in reflectivity of the two adjacent features causing the developed photoresist material to reveal one adjacent feature but not the other.

Abstract: A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.

Abstract: An aqueous electrochemical etchant for etching metals in the presence of one or more metals not to be etched, the etchant including glycerol in the concentration range of 1.30 to 1.70 M, a sulfate compound having a sulfate ion concentration in the range of 0 to 0.5 M, and a phosphate compound having a phosphate ion concentration in the range of 0.1 to 0.5 M.

Abstract: A precision punch and die device for punching holes in a ceramic substrate and method of assembling the device. The device comprises a punch which moves relative to a substrate for punching a hole in the substrate and a die assembly including one or more precision die plates and support plates for guiding a punch and punching a substrate.

Abstract: A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.

Abstract: A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.

Abstract: An apparatus for abrading a substrate including a moveable abrading tool having a bur for abrading the substrate, a stage for supporting the substrate, and a height sensing device in communication with the abrading tool to determine a vertical position of the bur with respect to the substrate. Further disclosed is a method for abrading a substrate using the foregoing apparatus including moving the abrading tool across the substrate so as to abrade the substrate, determining the vertical position of the bur with the height sensing device, and communicating the vertical position of the bur to the abrading tool.

Abstract: An apparatus and a method for removing a bonded lid from a substrate of variable size including nesting jaws to support and secure the substrate; and gripping jaws to grip the lid; wherein, in operation, the gripping jaws pivot with respect to the nesting jaws and create a, peeling action which separates the lid from the substrate with minimum force and without damage to the substrate or attached semiconductor devices.

Abstract: A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

Abstract: A fixture and process for assembly of semiconductor modules. Each module comprises a substrate and a cover attached to the substrate. The fixture comprises a baseplate adapted to accept the substrate and a spring-loading device containing a shape memory alloy spring engaging the cover. The shape memory alloy spring exerts a lesser force at room temperature and an elevated force at the bonding temperature of the bonding agent used to attach the cover to the substrate.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.