Patents Represented by Attorney Ira S. Matsil
  • Patent number: 5245543
    Abstract: An integrated circuit is designed by determined the devices comprising the integrated circuit and determining the desired parameters for each device. A flow of process steps is determined and the 1-D and 2-D simulations are performed on the process flow. The process steps are modified until the simulations determine that the desired parameters are met.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: September 14, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Michael C. Smayling, Georges Falessi
  • Patent number: 5240512
    Abstract: A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly the refrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semiconductor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: August 31, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Gordon P. Pollack
  • Patent number: 5240865
    Abstract: A thyristor (38) is formed over an insulating layer (44). A gate (70) is operable to create a depletion region through the semiconductor layer (46) in which the thyristor (38) is implemented in order to turn the thyristor off. Isolation regions (48, 52) prevent operation of the thyristor from affecting adjacent devices.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: August 31, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Satwinder Malhi
  • Patent number: 5236857
    Abstract: A method of forming an integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.
    Type: Grant
    Filed: October 30, 1991
    Date of Patent: August 17, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Eklund, Robert H. Havemann, Leo Stroth
  • Patent number: 5235335
    Abstract: A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.
    Type: Grant
    Filed: June 2, 1992
    Date of Patent: August 10, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Richard K. Hester, Khen-Sang Tan, Michiel de Wit
  • Patent number: 5231296
    Abstract: A thin film transistor and method for forming the same are disclosed. The transistor comprises a gate conductor (14) and a gate insulator (16). A semiconductor channel layer (18) is formed adjacent the gate insulator (16). A mask block (22) is formed covering a channel region (30) in the channel layer (18). A source region (26) and a drain region (28) are formed in the channel layer (18) adjacent opposite ends of the mask block (22). Conductive bodies (32) and (34) are formed in contact with source region (26) and drain region (28), respectively. Electric contacts (42) and (44) are then formed in contact with conductive bodies (32) and (34), respectively.
    Type: Grant
    Filed: November 7, 1991
    Date of Patent: July 27, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Mark S. Rodder
  • Patent number: 5225700
    Abstract: An electrically-erasable, electrically-programmable read-only memory cell (676) is formed at a face of a semiconductor layer (152) having a first conductivity-type and includes a tunnel diode doped region (688) of a second conductivity-type opposite said first conductivity-type formed at the face of semiconductor layer (152). A first highly doped region (688) of the second conductivity-type and a second highly doped region (702) also of the second conductivity-type are formed in the face of semiconductor layer (152) spaced by a sense transistor channel region (696). At least one of the first highly doped region (688) and second highly doped region (702) is spaced from tunnel diode region (688). A thin tunnel insulator (732) is formed on the face of semiconductory layer (152) over tunnel diode doped region (688) and a gate insulator (218) is formed on the face of semiconductor layer (152) over sense transistor channel region (696).
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: July 6, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Michael C. Smayling
  • Patent number: 5221635
    Abstract: A field-effect transistor (10, FIG. 2) possesses improved electrostatic discharge characteristics. The transistor (10), formed in a p-type semiconductor substrate, comprises a gate (16) that forms a channel between two adjacent n-regions (12 and 14). At least one of the n-regions (12) has an n-well (22) below and centered about a contact pad (18). The n-well (22) has a second lower concentration of n-type impurities than either of the n-regions.
    Type: Grant
    Filed: December 17, 1991
    Date of Patent: June 22, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Charvaka Duvvury
  • Patent number: 5219783
    Abstract: A method of forming doped well regions in a semiconductor layer 14 is disclosed herein. At least one n-doped region 30 and at least one p-doped region 36 are formed in the semiconductor layer 14. The n-doped region 30 is separated from the p-doped region 36 by a separation region 39. An oxide layer 32 (38), for example silicon dioxide, is formed over the n-doped region 30 and p-doped region (36) but not over the separation region 39. The semiconductor layer 14 is then heated (e.g., at a temperature of less than 1150.degree. C.) in a nitridizing environment such as ammonia. Other structures and methods are also disclosed.
    Type: Grant
    Filed: March 20, 1992
    Date of Patent: June 15, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Mehrdad M. Moslehi
  • Patent number: 5217915
    Abstract: A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.
    Type: Grant
    Filed: April 8, 1991
    Date of Patent: June 8, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Mashashi Hashimoto, Shivaling S. Mahant-Shetti
  • Patent number: 5215931
    Abstract: A semiconductor over insulator transistor is provided preferably of a lightly doped drain ("LDD") profile. LDD transistor (74) includes a semiconductor mesa (76) formed over an insulating layer (94) which overlies a semiconductor substrate (96). Semiconductor mesa (76) includes a source region (78) and a drain region (80) at opposite ends thereof. A body node (82) is disposed between source and drain regions (78,80). A low resistance contact region (98) lies along substantially the entire width of body region (82) and contacts a vertical contact which permits electrical contact from the top surface of semiconductor mesa (76) to low resistance contact region (98). Low resistance contact region (98) may be extended to fully underlie source region (78) such that the vertical contact may be moved away from body node (82).
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: June 1, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 5216750
    Abstract: Preferred embodiments include systems with neural network processors (58) having input encoders (56) that encode integers as binary vectors so that close integers encode as close binary vectors by requiring adjacent integers have encoded binary vectors that differ in a fixed fraction of their bits.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: June 1, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Derek J. Smith
  • Patent number: 5216270
    Abstract: A non-volatile memory cell 10 can be fabricated by doping a semiconductor substrate 8 to form source 12 and drain 14 such that at least one small undoped region remains in source 12. A first insulation layer 26a is formed over the source 12 such that the thickness of the layer is less over the undoped region than the doped region while insulation regions 26b and 20 are simultaneously formed over the drain 14 and channel 16 regions. The insulation layer 26a formed above the undoped region of the source 12 is etched to form a tunnel window 28 and then a thin insulation layer is formed over the tunnel window 28. A conductive floating gate 16 is formed over a portion of the first insulation layer 26a which includes the tunnel window 28, over the channel region 16 and over a portion of the second insulation region 26b. Next, an insulation region 24 is formed over the floating gate 16 and a control gate 18 is formed over the insulation region 24. Other structures and methods are also disclosed.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: June 1, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Cetin Kaya, Howard L. Tigelaar, Mauzur Gill
  • Patent number: 5206533
    Abstract: A static memory cell comprises a first PMOS transistor including a drain 319, a channel 344, a source 317, and a lightly doped drain 360 and a first NMOS transistor including a source 323, a channel 346, and a drain 321. A first gate 334 insulatively overlies the channel 344 and the lightly doped drain region 360 of the first PMOS transistor as well as the channel 346 of the first NMOS transistor. The memory cell also includes a second PMOS transistor which in turn includes a drain 327, a channel 362, a source 325, and a lightly doped drain 364 and a second NMOS transistor which includes a source 323, a channel 368, and a drain 329. A second gate 338 insulatively overlies the channel 362 and the lightly doped drain region 364 of the second PMOS transistor and the channel 368 of the second NMOS transistor.
    Type: Grant
    Filed: June 24, 1991
    Date of Patent: April 27, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 5202576
    Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).
    Type: Grant
    Filed: June 25, 1991
    Date of Patent: April 13, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: David K. Liu, Man Wong
  • Patent number: 5200919
    Abstract: A field effect transistor memory cell having a selectable threshold voltage is formed in a semiconductor layer (18). An n-channel electrically-erasable, electrically-programmable read-only memory cell (12) is formed and includes a source (14) and a drain (16) separated by a channel (20), a tunneling window (22) adjacent drain (16), a floating gate (24) and a control gate (26) capacitively coupled to channel (20). N-channel memory cell (12) is operable to charge and discharge floating gate (24) by Fowler-Nordheim tunneling upon the application of voltages to control gate (26) and drain (16). A p-channel field effect transistor (30) is formed and includes a source (34) in a drain (36) spaced by a channel (38). Floating gate (24) is insulatively disposed adjacent channel (38) such that the conductance of channel (38) is controlled by floating gate (24). A threshold control circuit (76) is provided for biasing channel (38) of p-channel field effect transistor (30) in relationship to control gate (26).
    Type: Grant
    Filed: July 15, 1991
    Date of Patent: April 6, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Cetin Kaya
  • Patent number: 5198710
    Abstract: A bi-directional digital noise filter will eliminate glitches of one delay while adding only one delay to the information signal. A first embodiment digital noise glitch filter 8 comprises a two asymmetric delay elements 10 and 12 connected in series. The first element 10 has a delay of equal duration as the longest glitch to be filtered and the second element 12 has a delay twice as long as the first delay. A third asymmetrical delay circuit 20 coupled in parallel the other delays has the first delay. Other systems and methods are also disclosed.
    Type: Grant
    Filed: May 30, 1991
    Date of Patent: March 30, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 5196703
    Abstract: A method of detecting the intensity of radiation emanating from an object 116 relative to a background level at a pixel detector 120 is disclosed herein. A resistive element 122 with a resistance dependent upon the intensity of radiation impinging the detector 120 and having first and second terminals is provided along with an integration element 124 coupled to the first terminal of the resistive element. The first terminal is set to a reference voltage. The radiation is then defocused such that the radiation impinging the detector 120 is proportional to the background radiation level and a first voltage is applied to the second terminal of the resistive element 122 such that the integration element 124 discharges to a background voltage level.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: March 23, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: William F. Keenan
  • Patent number: 5184398
    Abstract: A system 20 for measuring the sheet resistance of a conductive layer on the top surface of a semiconductor wafer 22 is disclosed herein. In one embodiment, the system includes a chuck 30 electrically coupled to the backside surface of the wafer 22. The chuck 30 is capable of supporting the wafer 22 electrostatically. A signal source 40 provides an excitation signal to the wafer 22 and circuitry for monitoring an induced signal is provided. The sheet resistance on the top surface of the wafer 22 is determined from the measurements of the excitation and induced electrical signals. Other systems and methods are also disclosed.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: February 9, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Mehrdad M. Moslehi
  • Patent number: 5182222
    Abstract: A method is provided for manufacturing a semiconductor device at a face of a semiconductor layer having a first conductivity type. Over the semiconductor layer and insulating therefrom a gate conductive layer is formed, which has a predetermined pattern defining an opening. A well of a second conductivity type is then implanted into the face of the semiconductor layer by self-aligning to the sidewall of the gate conductive layer. A first surface region of the first conductivity type is formed within the well and self-aligned to the sidewall of the gate conductive layer. A sacrificial sidewall layer is formed in the opening which defines a second narrower opening, so that a subsurface region of the second conductivity type may be formed within the well self-aligned to the sacrificial sidewall layer. A second surface region of the second conductivity type is then formed substantially within the first surface region and self-aligned to the sacrificial sidewall layer.
    Type: Grant
    Filed: June 26, 1991
    Date of Patent: January 26, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Satwinder Malhi, Taylor R. Efland