Abstract: A thyristor (38) is formed over an insulating layer (44). A gate (70) is operable to create a depletion region through the semiconductor layer (46) in which the thyristor (38) is implemented in order to turn the thyristor off. Isolation regions (48, 52) prevent operation of the thyristor from affecting adjacent devices.

Abstract: A sample and hold circuit (24) is provided which includes an input terminal (36) for receiving a time varying input voltage. A first capacitor (14) maintains a first voltage corresponding to a sample of said time varying input voltage. A switch (12) having a control terminal (20) is operable to sample the input voltage by coupling input terminal (36) to first capacitor (14) in response to a sampling signal provided at control terminal (20). At least one second capacitor (58, 86) is provided for maintaining a preselected voltage. Circuitry (40, 42, 68, 106) is provided for selectively applying the sampling signal to control terminal (20) of switch (12) by impressing at least the preselected voltage maintained by second capacitor (58, 86) on control terminal (20).

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Abstract: One embodiment of the present invention is a one transistor DRAM cell having enhanced capacitance and minimized soft error rate by providing an ungrounded cell capacitor plate which is insulated from the substrate. The structure includes a vertical transistor on the sides of a vertical depression or trench in a substrate. In the bottom of the trench, a memory cell capacitor is fabricated. This capacitor includes a conductive polycrystalline silicon post through the middle of the capacitor, thereby increasing the surface area of the capacitor plates. This increases the capacitance of the memory cell capacitor.The ungrounded plate of the memory cell capacitor is fabricated in the trench and is insulated from the substrate. This ungrounded plate is connected to the vertical transistor via a polycrystalline silicone plug. Thus this embodiment of the present invention reduces soft error rate by providing a fully insulated ungrounded memory cell capacitor plate.

Abstract: Optically pumped coupled quantum well devices are disclosed. The devices store bits as carrier packets in depressions in the conduction and/or valence band(s) of a single crystal; the band between the depressions is sloped in a common direction which provides unidirectionality. The carrier packets are shifted from depression to depression by optically exciting the carriers and relying on the arrangement of depressions and band slopes; the excitation is conveniently performed by laser illumination. The depressions may be sufficiently small to discretize the energy levels and thereby permit the partitioning of the depressions into groups with each group having depressions of substantially the same energy level structure. The carriers in depressions of one group can then be selectively excited by illumination with a laser or narrow band monochromatic incoherent light source tuned to the energy level structure; this allows multiphase operation of the shifting function.

Abstract: An improved SOI structure 40 is provided. SOI structure 40 includes a semiconductor mesa 42 formed over a buried insulating layer 46 which overlies a substrate 48. Sidewall insulator regions 50 and 52 are formed along sidewalls 54 and 56, respectively, of semiconductor mesa 42. Sidewall spacers 62 and 64 are formed along sidewall insulator regions 50 and 52, respectively. Sidewall spacers 62 and 64 each include respective foot regions 66 and 68. Foot regions 66 and 68 effectively shift undercut areas 74 and 76 laterally away from semiconductor mesa 42.

Abstract: An N-bit conditional sum adder 8 includes first and second conditional sum adders 10a and 10b. Each of the adders may be built from a plurality of one-bit conditional sum adders 110. In one embodiment, each one-bit adder 110 comprises a XNOR gate 50, a XOR gate 52, a NAND gate 54 and a NOR gate 56. The carry outputs CO.sub.a and CO.sub.b of the first conditional sum adder 10.sub.a are coupled to BiCMOS drivers 12 and 14 which in turn are coupled to the select inputs of a plurality of multiplexers 16 and 18. The multiplexers may be CMOS multiplexers built from transmission gates.

Abstract: A pipelined Fast Fourier Transform (FFT) architecture includes a memory for storing complex number data. A pipelined data path is coupled to the memory for accessing R complex number data therefrom, for computing an FFT butterfly, and storing R results from the FFT butterfly computation in the memory during one pipeline cycle.

Abstract: A scanning electron microscope (28) is connected to a test structure (48) formed on a semiconductor wafer. The test structure (48) comprises a plurality of first parallel structures (54) and a plurality of second parallel structure (56) transverse to and interlocking with the first structures (54). An island (60) is formed within a grid (58) formed by the structures (54-56) and is separated therefrom. An electron beam (38) from the scanning electron microscope (28) is aimed at the structure (48) and secondary electrons emitted therefrom are visually displayed on a monitor (44). The visual display (47) provides information on whether the island (60) is electrically separated from the mesh (58) or shorted thereto by comparing the intensity of the various islands (60).

Abstract: A semiconductor over insulator transistor is provided preferably of a lightly doped drain ("LDD") profile. LDD transistor (74) includes a semiconductor mesa (76) formed over an insulating layer (94) which overlies a semiconductor substrate (96). Semiconductor mesa (76) includes a source region (78) and a drain region (80) at opposite ends thereof. A body node (82) is disposed between source and drain regions (78,80). A low resistance contact region (98) lies along substantially the entire width of body region (82) and contacts a vertical contact which permits electrical contact from the top surface of semiconductor mesa (76) to low resistance contact region (98). Low resistance contact region (98) may be extended to fully underlie source region (78) such that the vertical contact may be moved away from body node (82).

Abstract: An EEPROM memory cell having sidewall floating gates (28, 28a, 28b) is disclosed. Sidewall floating gates (28, 28a, 28b) are formed on sidewalls (30, 32) of a central block (22). Spaced apart bit lines (36, 36a, 36b) are formed to serve as memory cell sources and drains. Sidewall floating gates (28a, 28b) are capable of being programmed independently of one another. When control gate (18) is actuated and either bit line (36a) or bit line (36b) is used to read the device, four separate memory states may be identified depending on whether either, neither or both of the sidewall floating gates (28a, 28b) have been programmed.

Abstract: A multi-point non-invasive, real-time pyrometry-based temperature sensor (200) for simultaneously sensing semiconductor wafer (22) temperature and compensating for wafer emissivity effects. The pyrometer (200) measures the radiant energy that a heated semiconductor wafer (22) emits and coherent beams of light (224) that the semiconductor wafer (22) reflects. As a result, the sensor (200) generates accurate, high-resolution multi-point measurements of semiconductor wafer (22) temperature during a device fabrication process. The pyrometer (200) includes an infrared laser source (202) that directs coherent light beam (203) into beam splitter (204). From the beam splitter (204), the coherent light beam (203) is split into numerous incident coherent beams (210). Beams (210) travel via optical fiber bundles (218) to the surface of semiconductor wafer (22) within the fabrication reactor (80). Each optical fiber bundle (218) collects reflected coherent light beam and radiant energy from wafer (22).

Abstract: An electron beam imaging system (10) includes a photoemitter plate (12). An optical image beam (15) is directed through a pattern mask (18), which is imaged onto the photoemitter (12). The photoemitter (12) emits electrons from those unmasked regions illuminated by the optical image beam, emitting an extended-source electron beam that carries the mask image. The extended-source electron beam is focused (34) onto a device under fabrication (40), providing a single-stage electron lithographic patterning function. The optical source (16) is chosen so that the optical image beam energy is nearly identical to the work function for the photoemissive coating (14) of the photoemitter (12). As a result, the photoemitter (12) emits electrons with substantially zero kinetic energy, allowing the emitted electrons to be accelerated through the electron beam focusing elements (34) with very nearly identical electron velocities, thereby minimizing chromatic aberrations.

Abstract: A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.

Abstract: An improved local electrical interconnect device fabrication and method are provided. Reacted refractory metal contacts and local interconnect lines (54) and (56) are formed by reacting a deposited refractory metal layer (53) with selectively grown semiconductor regions (48) and (50). Regions (48) and (50) are formed after a masked ion implantation which forms loosely bonded surface regions (44) and (46) within field insulating regions (12). As a result of the ion implantation, semiconductor regions (48a) and (50a) are able to form over field insulating regions (12).

Abstract: A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species.

Abstract: A transistor for VLSI devices employs a phosphorus implant and lateral diffusion performed after the sidewall oxide etch to thereby reduce the impurity concentration and provide a graded junction for the reach-through implanted region between heavily-doped N+ source/drain regions and the channel, beneath the oxide sidewall spacer.

Abstract: A memory cell is disclosed which comprises a filament channel transistor and a ferroelectric capacitor formed on a surface of a semiconductor substrate. The transistor comprises a substantially cylindrical channel filament which is formed substantially perpendicular to the substrate surface between the surface and the capacitor. The capacitor comprises a storage layer which can be formed of a ferroelectric material such that the memory cell is nonvolatile. The storage layer may also comprise a high dielectric material such that the memory cell is operable as a dynamic random access memory cell.

Abstract: The invention discloses a method for selectively etching a first material at a faster rate than a second material, where both materials are incorporated on the surface of a semiconductor. The surface is disposed (step 100) in a plasma etcher. A reactant is flowed into the etcher (102). The etch agents are chosen so the chemical products created by a reaction between the etchant and the first material are volatile and the chemical products created by a reaction between the etchant and the second material are non-volatile. A reaction is then ignited (104) and the first material is etched (106). One embodiment discloses a method for forming a local interconnect.

Abstract: Preferred embodiments grow a first diamondlike film (114) on a silicon substrate (102). Diamond film (116) is then grown on diamondlike film (114), the diamondlike film (114) providing a high density of nucleation sites (108) for the diamond film (116). Diamond film growth is interrupted and a second diamondlike film (134) is grown to provide a second region of nucleation sites (128). Second diamond film (126) is grown from nucleation sites (128), resulting in a relatively thick diamond film (140) with relatively small crystal grains.