Abstract: A multiple DRAM cell trench structure provides increased cell capacitance. A deep trench (18) is formed in a P+ semiconductor substrate (10), with sufficient trench width to prevent the tapered trench sidewalls from pinching off at the bottom thereof. Plural memory cells are formed in the trench (18) to increase the cell density of the array. Field oxide strips (14, 15) are formed between conductive polysilicon bitlines (16, 38) and the P- substrate (12) to reduce capacitance and the soft error rate of the cells.

Abstract: A system for measuring the temperature of a semiconductor wafer 12 comprises a light source 14, a photodetector 20 which is operable to determine light intensity, and a mirror 18 in a predetermined fixed position from a beam splitter 16. The components are positioned such that light from the light source 14 impinges the beam splitter 16 and subsequently reflects off the mirror 18 and the wafer 12 and is received by the photodetector 20. Changes in the temperature of the wafer 12 are calculated based upon changes in the intensity of the received light which depends upon the expansion/contraction of the wafer. The absolute temperature may be calculated based on a known reference temperature and the changes in wafer 12 temperature. A second system and method for measuring the temperature of a semiconductor wafer which includes the use of a plurality of mirrors and two beam splitters is also disclosed.