Abstract: For error testing and diagnostics in EDP systems, particular storage elements (e.g., 6) are connected to form an addressable matrix which is coupled to a maintenance and service processor (5) or an external tester through the system bus (9). During normal operation, the logic subsystems (10), of which processors (1) and processing units consist, are connected by the storage elements. Through the system bus, the maintenance and service processor or the tester transfers addresses to the matrix and test data to the addressed storage elements from where they are fed to the logic subsystems which in turn respond to such test data, transferring the (partial) result data thus received to the storage elements. In the next step, the maintenance and service processor or the external tester causes the result data for error analysis and diagnostics to be fetched through the system bus from the storage elements reconnected in the form of a matrix.

Abstract: A data processor has a block-multiplexed system channel coupled to a processing engine and a byte-multiplexed bus coupled to multiple I/O devices. A multi-buffer adapter transfers data by cycle-steal (direct memory access) operations between the channel and the bus. The adapter has multiple buffers switchable to the channel in a burst mode by a channel interface and to the bus in a byte mode by a device-level interface.

Abstract: Alphanumeric CRT display has normal/reverse video attribute. In reverse video, the character dots are made wider than in normal video, to equalize the apparent width of the dots in the two modes.

Abstract: A regulated on-chip substrate-voltage generator circuit converts a single power supply input and ground potential into a negative potential. The negative potential is applied to the substrate of an integrated circuit upon which the substrate-voltage generator is formed. The substrate voltage generator includes a voltage oscillator connected to a charge pump device. A pair of depletion FETs forms a voltage divider circuit between the ground potential and the substrate potential. An amplifier, formed from depletion FETs, couples the voltage divider into the charge pump. The voltage divider and amplifier regulate the charge pump thereby maintaining tight control over the substrate voltage.

Abstract: Multi-level indexed indirect addressing is provided with matched pairs of prefix bytes and suffix values which can surround any instruction. Each prefix code is distinguishable from an instruction code. Counters keep track of indirection levels.

Abstract: A single-FET-per cell read/write memory having capacitor storage elements also contains a pattern of fixed, latent data represented by ion implants in some of the FETs. This pattern is loaded into the capacitors by addressing the cells with a voltage between the thresholds of the normal and the implant-modified FETs, so that some of the capacitors are discharged and others are not. Thereafter, the data may be read out, or overwritten with variable data, by addressing the cells with a voltage higher than both thresholds.

Abstract: An IC chip connects to a substrate by a pattern of pads arranged in single lines along the radial edges of segments of a polygon underlying the chip-linear conductors from the pads cross the outer edge of the segments in parallel groups. Wider power conductors can also be placed in the pattern.

Abstract: A clustered system of data-entry terminals includes a plurality of physically separate data-entry terminals coupled to a communications link in a cluster. Each of the terminals includes a programmable digital processor for transferring data and programs over the communications link. Each of the terminals further includes entry devices and display devices for communicating information between an operator and the programmable processor.

Abstract: Image rotate control circuitry buffers one column of display or video data which is subsequently printed along a horizontal print line. A video dot counter cycles each horizontal scan line while a print line counter cycles each vertical scan. Video data is entered into the buffer when the count in the video dot counter equals the count in the print line counter. After one refresh of the display the buffer contains one print line of data. This data is shifted from the buffer to the printer during the vertical retrace or vertical blank period of the display. The control circuitry sends a strobe signal to the printer for the print operation as a new column of data is being buffered during the next refresh of the display.

Abstract: A porcelain glazed metal bar has a rounded edge carrying a line of deposited print elements. Conductive lands deposited on both sides of the glazed bar connect the print elements to contacts for external circuitry.

Abstract: A memory-array sense amplifier includes a grounded-gate depletion-mode FET connected between a bit line and a sense node. Another FET connects a supply voltage VDD to the sense node when turned on by a clock phase signal. Further FETs form a latch circuit.

Abstract: A standalone point-of-sale terminal in a unitary physical package has input/output devices for communicating transaction data between the terminal and an operator, and also has a cash drawer. These devices and a direct-access storage are controlled by a programmable processor which executes low-level routines from read-only addressable memory and serially replaceable high-level applications programs from read/write addressable memory. Both applications programs and transaction data are stored on a single non-volatile, removable storage medium.