Patents Represented by Attorney, Agent or Law Firm James H. Morris
  • Patent number: 6835629
    Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: December 28, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventor: Piero Fallica
  • Patent number: 6834357
    Abstract: An application program runs on an embedded processor connected via a link to a host. When the application program identifies a need for communication over said link, it reads a pointer location to see whether its contents represent a valid address in memory, and if so the program calls that address. It then checks the code at the address to see whether an entry point is stored there, and if so uses that entry point to access a subroutine enabling communication over the link.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: December 21, 2004
    Assignee: STMicroelectronics Limited
    Inventor: Mark Phillips
  • Patent number: 6831338
    Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive layer extending above the substrate between the second region and the wall. The component includes a third N-type region of high doping level formed in the substrate under the portion of the layer substantially halfway between the external periphery of the second region and the internal periphery of the wall. This third region is contacted by a field plate extending on either side of the third region in the direction of the wall and of the third region.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: December 14, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Patent number: 6830951
    Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including at least the following phases: implanting active areas on a semiconductor substrate to obtain at least a first, a second and a third integrated region of corresponding photosensors; forming a stack of layers of different thickness and refractive index layers over the photosensors to provide an interferential filter for said photosensors. The stack is obtained by a deposition of a first oxide stack including a first, a second and a third oxide layer over at least one photosensor; moreover, this third oxide layer is obtained by a deposition step of an protecting undoped premetal dielectric layer.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: December 14, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Laurin, Matteo Bordogna, Oreste Bernardi
  • Patent number: 6832334
    Abstract: A computer system includes instruction fetch circuitry, decode circuitry to decode instructions and identify any registers to be used and dispatch circuitry to dispatch instructions to one or more execution units, said system including emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions, the computer circuitry further comprising a register watch store for identifying one or more registers to be watched, comparator circuitry for comparing registers identified by said decode circuitry with registers identified in said register watch store and providing a hit signal for hits in the comparison, and instruction insertion circuitry responsive to hit signals to insert in the instruction sequence to an execution unit a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data regist
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: December 14, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Laurent Wojcieszak, Isabelle Sename, Stephane Bouvier
  • Patent number: 6822532
    Abstract: A suspended stripline device and method for manufacturing thereof. The device includes first and second conductive traces disposed on a dielectric substrate, each of the first and second conductive traces having a first edge and a second edge, and a housing at least partially surrounding the dielectric substrate, wherein the second edge of each of the first and second conductive traces includes at least one outwardly extending protrusion, the size and orientation of which may be selected so as to compensate for unequal even and odd mode propagation velocities through the suspended-stripline device. The device may be packaged by folding solder-coated tabs, provided on the housing, around the dielectric substrate and heating the device such that the solder melts causing the housing to be secured to the substrate.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: November 23, 2004
    Assignee: Sage Laboratories, Inc.
    Inventors: John R. Kane, Richard J. Garabedian
  • Patent number: 6818953
    Abstract: The forming of an integrated circuit including at least one element of electronic protection of the circuit formed of at least one switch for short-circuiting supply conductors arranged in a rail, the switch being integrated in the rail, under said conductors.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: November 16, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Alexandre Malherbe, Fabrice Blisson
  • Patent number: 6816821
    Abstract: A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing system.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: November 9, 2004
    Assignee: STMicroelectronics Limited
    Inventor: Geoff Barrett
  • Patent number: 6815779
    Abstract: An integrated circuit including a vertical power component having a terminal formed by a chip substrate of a first conductivity type, a control circuit thereof, the control circuit isolated from the substrate by an isolation region of a second conductivity type, and a protection structure against polarity inversion of a substrate potential. The protection structure includes a first bipolar transistor with an emitter connected to said isolation region and a collector connected to a reference potential input of the integrated circuit, a bias circuit for biasing the first bipolar transistor in a reverse saturated mode when the substrate potential is higher than the reference potential, and a second bipolar transistor with an emitter connected to the substrate and a base coupled to the isolation region for coupling the isolation region to the substrate through a high-impedance when the substrate potential is lower than the reference potential.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: November 9, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Torres, Sergio Tommaso Spampinato
  • Patent number: 6816559
    Abstract: An FSK transceiver circuit, including a controlled oscillator used, in a transmission mode, to modulate a carrier by frequency shifts according to a binary transmission signal present on an input pin of the circuit, the shift amplitude being determined by an adjusting element connected to an adjusting pin of the circuit; two mixers connected to receive a reception signal present on a receive pin and, respectively, two carriers in phase quadrature of the controlled oscillator that, in receive mode, receives no modulating signal; and a demodulator connected to the outputs of the mixers via respective filters, the output of one of the filters being accessible from the outside by a circuit test pin.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: November 9, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Sirito-Olivier, Christophe Dugas
  • Patent number: 6812531
    Abstract: Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a s
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Livio Baldi, Paolo Ghezzi
  • Patent number: 6809383
    Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: October 26, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ferruccio Frisina
  • Patent number: 6807626
    Abstract: A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: October 19, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Andrew Cofler, St├ęphane Bouvier, Bruno Fel, Laurent Ducousso
  • Patent number: 6806536
    Abstract: An electronic chip formed of at least one second elementary chip set in first elementary chip so that the surfaces of the elementary chips are substantially in the same plane wherein the first elementary chip is formed of a heterogeneous substrate including a surface layer above a layer of different doping and defining at least one cavity extending the entire thickness of the second layer and at least one metal interconnection level connecting the at least one second elementary chip to the first elementary chip.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: October 19, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Yvon Gris
  • Patent number: 6804698
    Abstract: A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: October 12, 2004
    Assignee: STMicroelectronics Limited
    Inventors: Neil Richards, Gajinder Singh Panesar, John Carey, Peter Thompson
  • Patent number: 6791610
    Abstract: A focal plane array sensor includes optics located along an optical path, for transmitting radiation. A focal plane array and integrated circuit, located along the optical path for receiving the transmitted radiation, responsively produces image signals from the transmitted radiation. The integrated circuit includes apparatus for converting the image signals into digital image data at digital image data outputs.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: September 14, 2004
    Assignee: Lockheed Martin IR Imaging Systems, Inc.
    Inventors: Neal R. Butler, Charles M. Marshall
  • Patent number: 6791808
    Abstract: A clipping device intended for absorbing current peaks from 1 to 10 amperes, formed of a vertical NPN transistor, having an unconnected base, an emitter connected to a terminal on which positive voltage peaks are likely to appear, and a grounded collector, the transistor parameters being set so that it exhibits a negative dynamic resistance.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 14, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Eric Bernier, Robert Pezzani
  • Patent number: 6784785
    Abstract: A method of transmission between two elements chosen from a terminal and a transponder, each element including an oscillating circuit, a modulator and a demodulator, including simultaneously performing a transmission in amplitude modulation of a signal transmitted from a first to a second element and a transmission of a signal from the second to the first element adapted to being submitted to a phase demodulation in the latter, and wherein the amplitude modulation rate is smaller than 100%.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: August 31, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Luc Wuidart, Michel Bardouillet, Jean-Pierre Enguent
  • Patent number: 6785642
    Abstract: A method is described for converting a data set for use with a digital model of a hardware cell into an expanded data set for use with an analog model of the hardware cell. The method including the steps of determining the signal required to drive one or more pins of said analog model by analyzing whether the signals used in said digital model are in a first category or a second category, said first category containing relatively simple signals and said second category containing relatively complex signals, and providing the signal required for the one or more pins in the analog model in dependence on said analysis.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: August 31, 2004
    Assignee: STMicroelectronics Limited
    Inventor: Peter Ballam
  • Patent number: 6784465
    Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: August 31, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy