Abstract: A method and a system of data transmission between a terminal for generating an electromagnetic field and a transponder, the terminal and the transponder each including an oscillating circuit forming an antenna, and the transponder including an electronic circuit adapted to absorbing and giving back power provided by the terminal field, the oscillating circuits of the transponder and of the terminal being capable of transmitting radio-electric signals of determined frequency, this method including causing a detuning of at least one of the oscillating circuits with respect to the determined frequency when the transponder and the terminal are very close to each other.

Abstract: An executable program is prepared from a plurality of object code modules, at least one of the object code modules including section data specifying a plurality of code sequences each associated with relocation instructions identifying condition parameters. Only one of the code sequences is selected for inclusion in the executable program, determined by whether the condition for that parameter is satisfied. A linker for preparing the executable program includes a stack, a relocation module for reading the relocations, carrying out the relocation operations and selecting code sequences for inclusion in the executable program in dependence on values taken from the stack, a section data module for holding section data which is subject to the relocation operations, and a program forming module for preparing executable programs. Also disclosed is a method of assembling an object code module such that the assembled object code module includes the conditional code sequences.

Abstract: A computer system with parallel execution pipelines and a memory access controller has store address queues holding addresses for store operations, store data queues holding a plurality of data for storing in the memory and load address storage holding addresses for load operations, said access controller including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits.

Abstract: A modelling tool for use in defining an ASP which receives as its input an input file which for each of a set of peripherals defines the functional attributes of that peripheral in a high level language with an input data structure and which generates from the input file, (i) an interface functions file, which defines the communication attributes of the peripheral with the processor and the functional attributes of the peripheral in a manner independent of any particular data structure, (ii) a test functions file which defines the communication attributes of the processor with the peripheral in a manner independent of any particular data structure, and (iii) a register definition file by allocating specific elements of the input data structure to predefined sectors of a register definition table.

Abstract: There is disclosed a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU and a communication bus providing a parallel communication path between the CPU and at least one of the module with logic circuitry. The integrated circuit device further comprises an external communication port connected to the bus, having an internal parallel format for connection to the bus. The external port further has an external signal having an external format less parallel than the internal format. Translation circuitry is provided to effect conversion between said internal and external formats. There is also disclosed a method of operating such a computer system.

Abstract: PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided.

Abstract: A method of testing integrated circuitry at a module and system level, in which an intermediate test, including multiple testing steps, is generated in a third programming language. The intermediate test is converted into an abstract representation of the testing steps. System and module level tests based on the abstract representation are generated in second and first respective programming languages. The integrated circuitry is then tested at system level with the system-level test and at module level with the module level test.

Abstract: Integrated circuitry including a clock circuit powered by a first power supply and a secondary circuit powered by a second power supply. The secondary circuit includes a control signal output for supplying a control signal to the clock circuit and a clock data output for outputting new clock data to the clock circuit.

Abstract: A line scan circuit for a CRT, including, in series across a switch, two oscillating circuits having the same time constant, each including, in parallel, a capacitor, a diode connected in antiparallel, and a series association of an inductor and of a voltage source, the inductor of a first one of the oscillating circuits being a scan coil of the CRT; an amplifier receiving a set-point voltage and using, as a feedback, a voltage taken from one of the oscillating circuits, and providing an adjustable voltage source to the second oscillating circuit.

Abstract: A method of forming separate buried layers close to one another in a semiconductor component. This method includes the steps of forming, by implantation, doped areas in a semiconductor substrate; performing an anneal just sufficient to eliminate crystal defects resulting from the implantation; depositing an epitaxial layer; digging trenches delimiting each implanted region; and annealing the buried layers, the lateral diffusion of which is blocked by said trenches, said trenches being deeper than the downward extension of the diffusions resulting from said implantations.

Abstract: An executable program is prepared from a plurality of object code modules, each object code module including special relocations that have a type field for identifying the nature of a function to be implemented by the special relocation. The function is selected from a plurality of arithmetic and logical functions. A method of preparing the executed program includes reading the special relocations, determining from the type field the nature of the function to be implemented, carrying out the selected arithmetic or logical function to generate a result value and using the result value in a subsequent special relocation operation. The method may be executed by a linker having a relocation module for reading the special locations and carrying out the relocation operations.

Abstract: An executable program is prepared from a plurality of object code modules, each module including relocation instructions having an instruction format which includes a classification field for holding a relocation class indicator and a set of relocation fields for holding relocation data. The meaning of the relocation data depends on the class indicator. The instruction format is common to first and second classes of relocations. The executable program is prepared by reading the relocation instructions and determining from the relocation class indicator the class of the relocation instruction and executing the relocation operations on section data in dependence on the class of relocation instruction indicated by the relocation class indicator.

Abstract: An integrated circuit with a D.C./D.C. internal voltage regulator, including at least two power stages of the regulator, having respective terminals of connection to a supply voltage connected to distinct pads of the integrated circuit, and a single control stage.

Abstract: A decode unit (20) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry (50-60) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX6,MUX7) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector (70) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.

Abstract: A monolithic photodetector including a photodiode, a precharge MOS transistor, a control MOS transistor, a read MOS transistor, and a transfer MOS transistor, the photodiode and the transfer transistor being formed in a same substrate of a first conductivity type, the photodiode including a first region of the second conductivity type formed under a second region of the first conductivity type more heavily doped than the first region, and above a third region of the first conductivity type more heavily doped than the substrate, the first region being the source of the second conductivity type of the transfer transistor, the second and third regions being connected to the substrate and being at a fixed voltage.

Abstract: A method for forming a component in a portion of a semiconductor substrate on insulator delimited by a lateral wall separated by an insulating layer from a peripheral region internal to the portion and heavily doped of a same first conductivity type as the substrate. A conductive plate is formed at the same time as the wall, on a layer of protection of the substrate surface, in electric contact with the peripheral region, the plate extending above said peripheral region towards the inside of the portion with respect to the wall, beyond the location above the limit between the peripheral region and the substrate.

Abstract: A current source circuit is described for generating control current. The circuit is capable of generating a very accurate reference current and in particular dealing with the problem which can arise from injected noise. A feedback loop is implemented to reject the charge injection noise.

Abstract: A method and a memory controller for controlling a DRAM including a memory plane formed with an array of memory cells and at least two cache registers. An access request including a page address, a column address, a write or read order, a possibly data to be written is received. The page address of the current request is compared with the page address of the preceding request and, if they are different, the controller stores the current request page in one non-used of the cache registers, preferably that which has not been used last.

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device via an adapter device; the integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU, the integrated circuit further comprising an external communication port connected to the said bus on the integrated circuit chip, the port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device being connected to the external communication port with the first external format and to the external computer with a second external format having a higher latency than the first external format, the adapter device having an interface for translating between the first external format and the second external format; t

Abstract: A device for identifying a determined repetitive sequence of predetermined signals arriving on a modem. The device includes a delay circuit so that all the words of a sequence are simultaneously present; a combination circuit for providing a combined word; a circuit for calculating the modulus of each combined word and for comparing this modulus with a threshold; a circuit for counting clock pulses corresponding to the rate at which words arrive; a circuit for inhibiting the counting circuit when the modulus of the combined word is lower than the threshold; and a circuit for providing an identification signal when a predetermined number of clock signals is counted.