Abstract: A method and apparatus for forming silicon spheres (40) from irregular-shaped particles (38) for use in solar cells are disclosed. The apparatus (10) generally comprises a vertically aligned cylindrical chamber (12) having an abrasive lining (32) integrally formed therein. The abrasive lining (32) is preferably a silicon carbide material. A gas source (36) is tangentially injected into the chamber (12) to create an gas vortex inside the chamber (12). This vortex induces the repeated collision of the particles (38) against the abrasive lining (32) to eventually form the silicon spheres (40) and simultaneously sizing the silicon spheres (40).

Abstract: A dynamic random access memory cell has a storage capacitor and an access transistor formed on the sidewalls of a trench etched into the face of a silicon bar. The storage capacitor uses the sidewalls of the trench as the storage node, and uses a polysilicon plug as a common or grounded node. This polysilicon plug is part of a grounded field plate that surrounds the cell on the face and functions to provide isolation between cells. The channel of the access transistor is formed in a minor trench using the upper part of the sidewall of only one side of the major trench; an upper edge of the capacitor storage node functions as the source region of the transistor, while a buried N+ region on the face adjacent the trench is the drain. The gate of the transistor is a conductor extending along the face over the field plate except where it extends down into the minor trench at the channel area.

Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.

Abstract: A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both.

Abstract: An automatic test pattern generator and process assigns value-strength number to selected nodes representing the electrical characteristic strength of integrated circuits including field effect transistors and the logic state values at those nodes. These value-strength numbers become sensitized to the inputs of the selected node and become propagated to outputs of the selected node for establishing patterns for test signals. The test signals later become used in chip testers for determining good and bad integrated circuit chips. The value-strength numbers also become used in dynamic testing of the integrated circuit nodes by using clock signals of the integrated circuit to establish a transition at a start node of a test path. Within a known clock period later, the transition should become captured at an end node of the test path.

Abstract: An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio.

Abstract: An ESD protection device includes a PNPN type device disposed between the input pad (12) and ground. A first P-layer (48) is disposed in an N-type well (46) which is formed in a P-type layer (44). A second N-region (52) is provided for connection to ground. This provides an SCR which can be turned on by avalanching the intermediate PN junction (32) to place the device in a regenerative mode for positive transients. For negative transients, a P+ region (54) is provided in P-layer (44) to bypass a PN junction (34) and a N+ region (50) is defined in the N-type region (46) to bypass PN junction (30). This provides a forward-biased diode for the negative transient.

Abstract: The disclosure relates to a complex circuit composed of a circuit board which is formed of crystalline elemental silicon in the form of a slice and circuit component in the form of semiconductor integrated circuits thereon which are preferably formed of a Group III-V compound. Signals from each of the integrated circuits are transmitted to other integrated circuits on the board or externally of the board either by conventional printed conductors on the board or, preferably, by means of a laser formed in each integrated circuit at each output terminal thereon which transmits light signals along light conducting members in the silicon board to photo responsive elements at the input locations on other ones of the integrated circuits on the board for external to the board. The light signal is transferred from an integrated circuit output to an integrated circuit input or to a device external to the board by means of light conducting members.

Abstract: A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of the first channel layer and an insulating layer is formed on the surface of the first source/drain layer. A second source/drain layer of the second conductivity type is formed on the surface of the insulating layer and a second channel layer of said first conductivity is formed on the surface of the second source/drain layer. A third source/drain layer of the second conductivity type is formed on the surface of the second channel layer. Gate circuitry is vertically disposed on an edge perpendicular to the plane and adjacent to the first and second channel layers and insulated therefrom.

Abstract: An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shared drain region (16), with a corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (PlA). This floating gate channel section (32a/PlA) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the corresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD).

Abstract: A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.

Abstract: A plasma dry etch process for etching deep trenches in single crystal silicon material with controlled wall profile, for trench capacitors or trench isolation structures. HCl is used as an etchant under RIE conditions with a SiO.sub.2 hard mask. The SiO.sub.2 hard mask is forward sputtered during the course of the Si etch so as to slowly deposit SiO.sub.x (x<2) on the sidewalls of the silicon trench. Since the sidewall deposit shadows etching at the bottom of the trench near the sidewall, the effect of this gradual buildup is to produce a positively sloped trench sidewall without "grooving" the bottom of the trench, and without linewidth loss. This process avoids the prior art problems of mask undercut, which generates voids during subsequent refill processing, and grooving at the bottom of the trench, which is exceedingly deleterious to thin capacitor dielectric integrity.

Abstract: An input circuit for an integrated circuit furnishes a level shifting buffer portion adjacent a respective bond pad carried at the margin of the substrate while furnishing a clocked or latched portion adjacent the internal circuit of the integrated circuit. A lead extending from the level shifting or buffer portion to the clocked or latched portion carries the external signal applied to the bond pad and level shifted by the level shifting or buffer portion. The lead is subject to the parasitic resistance and capacitance of the integrated circuit. A multiplexer can be used to select among the level shifting portions for applying a single signal to the clocked portion and the clocked or latched portion can be part of a larger latch that receives plural signals for transmission to the internal circuit at appropriate times.

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

Abstract: A recoverable virtual memory for a computer system takes periodic checkpoints which capture the state of the virtual memory. If a system failure occurs, the system can be rolled back to the checkpointed state and restarted. A mechanism for tracking which virtual pages are contained in the checkpointed state discards pages which have been modified since the checkpointed state was saved. Only versions of pages which are saved in the checkpointed state are used in the restore process.

Abstract: The abbreviated jump field of the present invention enables each instruction word within the data processing apparatus to cause an instruction sequence branch to one of a limited number of destinations. Each instruction word of the data processing apparatus includes a limited number of bits which are decoded to specify one of a small set of instruction destinations. One of the possible destinations is the normal default destination of the next instruction word. In addition a relatively large number of branch instructions have been found to specify a rather limited number of destinations. In the preferred embodiment of the present invention the limited number of bits of the abbreviated jump field is employed to specify one of these widely used destinations. The widely used destinations may include a return instruction, a conditional skip of execution of the next instruction and various error handling and error recovery routines.

Abstract: A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.

Abstract: A method of backside damaging a silicon semiconductor wafer by abrading the wafer in an abrasive powder is disclosed. The wafer is rotated or translated in the powder while the powder is being vibrated. A fixture holds one or more semiconductor wafers during the processing and allows the wafer to be rotated during processing if desired.

Abstract: An analog to digital converter system (10) is disclosed which comprises an SAR logic circuit (12) which controls capacitor array control switches (14) which themselves control a capacitor array (16). A top plate (18) of the capacitor array (18) is selectively coupled to a coarse comparator (24) and a fine comparator (26). The outputs of the coarse comparator (24) and the fine comparator (26) are input into an error correction circuit (28). In operation, the coarse comparator (24) is used to approximate a predetermined number of the most significant bits of the digital word to be output by the system (10) while the fine comparator (26) is used to approximate the remaining bits of the digital word. In this manner, the coarse comparator (24) alone is subjected to the high voltages which might cause errors as a results of the hysteresis effect in the threshold voltages of the MOSFETs used to construct the comparators.