Abstract: Preferred embodiments include a monolithic uncooled infrared detector array of bolometers fabricated over a silicon substrate (142); the bolometers include a stack (144) of oxide (146) TiN (148), a-Si:H (150), TiN (152), oxide (154) with the TiN forming the infrared absorbers and resistor contacts and the a-Si:H the resistor with a high temperature coefficient of resistivity. The resistor is suspended over the silicon substrate (142) by metal interconnects (154 and 156) and related processing circuitry is formed in the silicon substrate (142) beneath the resistor.

Abstract: A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have graded regions of gradually decreasing conductivity adjacent to the end of the channels. Thus the electric potential gradient at the ends of the channels is reduced, and impact ionization and hot carrier effects are avoided. The effective radius of the source (or drain) junction is increased, providing increased breakdown voltage.

Abstract: An apparatus (10) for real-time in-line monitoring of a material (26) comprises a blackbody source (12), a first set of reflective surfaces (17) and a second set of reflective surfaces (38). Electromagnetic radiation (16) is emitted from the blackbody source (12) into the first set of reflective surfaces (17), which directs the radiation to a flow stream or material (26) which is to be tested. The radiation passes through or is reflected from the material (26). A transmission spectrum, resulting from the passage of the radiation through the material (26) or the reflection from the material (26), is then received by the second set of reflective surfaces (38). The second set of reflective surfaces (38) diffracts the transmission spectrum (34-36) and focusses the diffracted spectrum onto a detector (52). The detector (52) provides transmission spectrum data to a microprocessor (58) for comparison to a characteristic spectrum of the material (26) for determination of the necessity of a process adjustment.

Abstract: A multilevel capacitor includes a selected number of interleaved conductive layers alternately of first and second conductivity types, each separated by interleaved dielectric layers, forming multilevel capacitor plates. The multilevel capacitor plates include at least first and second contact-edge areas, each including adjacent edges of each interleaved conductive/dielectric layer.A first electrode of the first conductivity type contacts the first contact-edge area, and a second electrode of the second conductivity type contacts the second contact-edge area. That is, these electrodes contact the corresponding edges of the interleaved conductive/dielectric layers within respective contact-edge areas.

Abstract: A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.

Abstract: An output buffer (26) comprises a plurality of transistors (28) arranged in parallel between an output pin (34) and ground (38). Resistors (30) are connected in series between the drain (30) of the transistors (28) and the output pin (34) to ensure that an electrostatic discharge generated through normal handling will be distributed substantially equally through each of the transistors (28), thus preventing damage to the output buffer (26).

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor 10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

Abstract: A method for forming a fuse for integrated circuits and a fuse produced therefrom is disclosed. The fuse (10) includes a substrate (12) having thick oxide layers (14) with a gap (16) formed therebetween. A second oxide layers (20), (14) is grown onto an N+ region (18). At the intersection between oxide layer (20), a sublithographic area is exposed and a dielectric layer (24) is formed therein. This structure is capable of reducing the capacitance between a polysilicon layer (26) formed thereon and the N+ diffusion region (18).

Abstract: DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructure on top of an underlying CMOS address circuit. The CMOS chip surface contains several processing artifacts that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.

Abstract: An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface in the bottom of the trenches which extend from one end to the other of the memory array.

Abstract: A memory cell which includes a pair of cross-coupled CMOS inverters. Each inverter has a capacitor coupled from its output to either the supply voltage or ground potential. One inverter has a capacitor coupled from its output to a voltage supply terminal and the other inverter has a capacitor coupled from its output to a ground terminal. Upon the application of power to the memory cell, the output of each inverter of the pair assumes a predetermined logic state thereby preventing dc current flow in either side of the cross coupled pair. In addition to providing for reduced power consumption, the selective cell assymetry provided makes possible a random access memory device that stores a fixed program at power up.

Abstract: A transistor cell (80) and enabling transistor (118) are provided. The transistor cell includes a trench transistor and a stacked transistor, with a cross-coupled capacitor between the gates of these transistors. The trench transistor includes a semiconductor region (98) functioning as a gate and first and second diffused regions (126, 135) as the source/drain regions therefor. The stacked transistor has a semiconductor layer (104) functioning as the gate and first and second doped regions (112, 114) within a semiconductor layer (110) functioning as the source/drain regions therefor. The stacked capacitor included herewith comprises semiconductor layer (104) and semiconductor region (98) having insulating layers (96, 102) therebetween.

Abstract: Conversion from a first set of logic levels, such as ECL levels, to a second set of logic levels, such as TTL, is performed by using a regulator (46) and is parallel to the circuit generating the first set of logic levels.

Abstract: A wire bonder for bonding semiconductor packages that require a deep access to bond between the semiconductor device bond pads and the bonding area on the package to avoid interference between the bond head and the package pins, the bonder including a bellows actuated wire clamp, a reverse venturi to remove slack from the bonding wire, and a lengthened bonding tool.

Abstract: An EPROM memory cell (32) stores information in a floating gate (44) which overlies a portion of a channel between a program drain (36) and a read drain (34). A control gate (46) has a lower segment (48) which overlies the portion of the channel not covered by the floating gate (44), and has an upper portion (50) overlying the floating gate (44). During a program operation, electrons flow from the read drain (34), acting as a source, to the program drain (36), and hot electrons are stored within the floating gate (44). During a read operation, electrons flow from the programming drain (36) to the read drain (34), and the majority of hot electrons drift to the control gate (46). Since the hot electrons do not enter the floating gate (44) during read operations, a higher driving current can be used, thereby increasing the speed at which the EPROM memory cell (32) is read.

Abstract: In execution of PROLOG-type programs, certain information is not saved at the time a procedure call is made. Such information is saved only if it becomes necessary, and at that time is saved in a known manner. If subsequent events make it unnecessary to save that certain information, the time required to do so has not been spent, thus improving system performance.

Abstract: A compound CMOS domino circuit is disclosed having a first input section (62) comprising input transistors (50, 52, 54) connected to a preliminary dynamic output node (66). A second input section (64) including input transistors (56, 58, 60) is connected to a preliminary output dynamic node (68) which is independent of the first dynamic node (66). Separate precharge devices (72, 74) precharge the respective dynamic nodes (66, 68) to a desired voltage. Separate discharge transistors (78, 80) operate in conjunction with the respective input sections (62, 64) to discharge the dynamic nodes (66, 68) A static output logic gate (70) includes inputs connected to the dynamic nodes (66, 68) and an output of the compound domino logic circuit.