Abstract: A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at least 50%.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data decription is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

Abstract: There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from negative voltage levels to positive voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.

Abstract: The disclosure relates to a CMOS flow process for formation of high and low voltage transistors simultaneously in a single semiconductor chip. The low and high voltage transistors share the same gate oxide thickness and the same polysilicon gate level. This is accomplished without any additional masking steps and through the use of a separate lightly doped drain for the high voltage N-channel devices. The sources of the high voltage N-channel devices are fabricated using the more heavily concentrated LDD implant normally used for the low voltage transistors. This minimizes the source resistance of the high voltage transistor which results in higher performance through improved saturated transconductance. From a high voltage capability point of view, the flow permits the realization of a single level polysilicon single gate oxide thickness low/high voltage CMOS process.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterened by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.

Abstract: A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposited over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).

Abstract: A graphics coprocessor designed to work in conjunction with a host graphic processor in a graphics system. The coprocessor is adapted to perform arithmetic calculations including matrix calculations. The matrix size is such that the intermediate results require more registers than are practical to include in the coprocessor. This has been solved by arranging for certain selected ones of the intermediate results to continue within the program execution from stage to stage and avoiding intermediate storage.

Abstract: A reconfigurable resource architecture enhances a test system's utilization by allowing product-mix dependent allocation of test system resources. The test system resources can be configured to test several device types with different pin counts simultaneously. The configuration can be changed to accommodate various product mixes based on pin count.

Abstract: The disclosure relates to a pointer for a three dimensional display wherein a scanned light beam is displayed upon a rotating display member rotating about a fixed axis for receiving and displaying the scanned light beam on a first surface thereof, fixed points in the display impinging upon the display member to display a harmonic motion along an axis passing through the scanned light beam in response to rotation of the display means. A beam of focussed light, preferably from a laser is modulated to synchronize with rotation of the display member to provide a visible point in the display at a predetermined location therein. A second embodiment provides an encoder, light conducting rod bundle and sensor to determine the three dimensional location of the point denoted by the pointer.

Abstract: A damping circuit is described for the antenna resonance circuit (28) of a radio transmitter-receiver (10) which in a transmitting phase transmits a time-limited high-energy interrogation pulse and in a receiving phase following the transmitting phase is ready to receive high-frequency response signals coming from a responder (26) which transmits said response signals as reaction to the reception of the interrogation pulse. In the damping circuit (24) a damping member (R5, R5, R6) is provided which is adapted to be connected to the antenna resonance circuit and disconnected therefrom. A switching means (T4, T5) on receiving a switching voltage applies the damping member (R4, R5, R6) to the antenna resonance circuit (28).

Abstract: A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.

Abstract: A test for screening integrated circuits with weak cells comprises storing a known pattern into the cells, interrupting the power to the cells, and comparing the data in the cells upon power-up with the data originally stored therein. The test may be repeated using the complement of the first pattern. Those devices which retain the stored pattern despite the power interruption may be classified as resistant to upset.

Abstract: A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into certain logic states to enable the device to be tested without programmning the device's logic array (22).

Abstract: A semiconductor device is disclosed in which a deposited non-oxide layer (44) overlies and physically contacts another non-oxide layer (38) so that no intervening oxide layer is present. The device is fabricated by performing an insitu etch and deposition process. In one embodiment, the device (36) is sealed in a LPCVD chamber (10) and etched using gaseous anhydrous hydrofluoric acid to remove an oxide (40) from one non-oxide layer (38). Then, without exposing the device to a water rinse or to the atmosphere, a chemical vapor deposition process applies the deposited layer (44) upon the other layer (38).

Abstract: A slice handling apparatus (10) is mounted on a robot arm (12) to provide automated processing of semiconductor slices (69). The slice handling apparatus (10) has three tines, a center tine (50) and two side tines (62). The side tines (62) are fixed to position, while the center tine (50) is moved in and out using a control field actuator (20). A Hall effect sensor (26) on the control field actuator (20) provides an electrical feedback to provide a firm gripping force with reduce damage to slice edges by sensitive control of the gripping force. The tines (50, 62) have locator pins (58) which hold the slice (69). The locator pins (58) have a tapered bottom portion (84) and a vertical holding portion (86). The tapered bottom portion (84) prevents the slice (69) from contacting the tines (50, 62) in the event that the slice handling apparatus (10) is not positioned at the exact vertical position desired.

Abstract: The memory array circuit this invention provides connection of segmented bitlines to bitline decoding circuitry while, at the same time, providing connection of combined wordlines wordline decoding circuitry. The segmentation and decoding connections permit faster speed of operation with minimal or no area penalty. The area penalty is avoided by driving common wordlines in each of the segments, effectively increasing the wordline pitch at the wordline decoder, while at the same time decreasing the number of wordline decodes required. The segmentation also permits location of the decoder circuit away from the signal and routing decode outputs.

Abstract: A transmission line driver circuit (10) includes a signal input (12). A first capacitor (28) stores a first voltage level corresponding to a first of two possible bit values of an input signal. A second capacitor (44) stores a second voltage level corresponding to a second of the possible bit values. First and second voltage supply sources (24, 42) are selectively and respectively coupled to the first and second capacitors (28, 44) for recharging these capacitors to their respective voltage levels. A transmission line (50) is coupled to an output of a switching circuit. The switching circuit is operable to couple the first capacitor (28) to the switching circuit output (34) in response to receiving an input signal of a first bit value. The switching circuit is further operable to couple the second capacitor (44) to the output (34) in response to receiving an input signal of a second bit value. The bit value is thereby propagated onto the transmission line (50).

Abstract: Described is an architecture for translating between ECL and TTL/CMOS signal levels in which the control signal applied to the translating circuitry is of the same type as the output signal of the device in which the architecture is used.