Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.

Abstract: A method of passivation of Hg.sub.1-x Cd.sub.x Te and similar semiconductors by surface oxidation (such as anodic) followed by chemical conversion of the oxide to either sulfide or selenide or a combination of both is disclosed. Preferred embodiments provide sulfide conversion by immersion of the oxide coated Hg.sub.1-x Cd.sub.x Te in a sodium sulfide solution in water with optional ethylene glycol and the selenidization by immersion in a solution of sodium selenide plus sodium hydroxide in water and ethylene glycol. Also, infrared detectors incorporating such sulfide and selenide passivated Hg.sub.1-x Cd.sub.x Te are disclosed.

Abstract: A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implants of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.

Abstract: A microelectronic device (10a) provides an improved capacitor (12a) having two plate members (22a, 26a) capacitively coupled via a dielectric layer (24). In accordance with the invention, contact portions (32a, 42a) have substantially twice the thickness of functional portions (28, 38) prior to etching oxide (16) to form contacts (18, 20). In this fashion, the total thickness of capacitor (12a) is minimized yet the thickness of contact portions (32a, 42a) is maximized. Hence, maximum thickness for etching purposes [to construct metal contact 18, 20)] is achieved. Thus the topographical profile of microelectronic device (10a) is essentially reduced to half that of the prior art while the necessary pre-etch thickness of contact portions (32a) and (42a) is maintained. Other pre-etch thickness proporations may be utilized between conductive layer subportions (34) and (36) and conductive layer subportions (44) and (46).

Abstract: An optically activated keyboard having key members, each with a key pad having illuminated symbols at the keypad surface and for contact with the finger of the operator. A plunger is secured to the key pad for operating a device to indicate which key has been depressed. In one embodiment of the present invention, the plunger is formed of light transmitting material to transmit light from the interior of the keyboard to the key pad. The key pad has a light transmissive portion with a symbol thereon which is illuminated by the light passing through the plunger to provide the desired illuminated symbol. As a second embodiment, the symbol can be disposed in the light conducting plunger or therebeneath whereby the light entering the transparent key pad is in the shape of the desired symbol in either a negative or a positive representation thereof to project the desired symbol from the key pad.

Abstract: There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from positive voltage levels to negative voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.

Abstract: A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

Abstract: A read only memory whererin information is encoded in the pattern of coupling of column lines to changes of quantum-coupled wells linked by resonant tunneling, which constitute rows. it is not strictly necessary that each chain of quantum wells itself constitute one row, but the extremely close packing density of the quantum wells nevertheless permits a very high row density.

Abstract: A test circuit for a logic device having ports. The test circuit includes a serial scan path for serially transferring externally generated test vectors from a serial test input to a serial test output. A storing circuit stores a data bit and has a node at which the data bit is stored. A first interface circuit interfaces the node with a first one of the ports for synchronous transfer of data from the logic device to the node. A second interface circuit interfaces the node with the serial scan path to tranbsfer data from the serial scan path to the node. A coupling circuit connects the storing circuit to a second of the ports to transfer a logic level responsive to the data bit to the logic device during test. Also the coupling circuit temporarily couples the data bit from the node to the serial scan path also during test.

Abstract: An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provided isolation of the cells during programming.

Abstract: A baseboard for orthogonal mounting of integrated circuit chips thereto is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.

Abstract: A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resitive circuitry which allow bootstrapped voltages.

Abstract: In accordance with the preferred embodiment of the invention, a cam-operated idler roller assembly maintains tension on a computer printer generated form as it advances through the print station of a computer printer. This invention provides a nip station that disengages on a print medium reversal to allow the form to be run in a reverse direction through the print station by means of a cam design that disengages the idler roller assembly from the drive roller. The cam design further allows the idler roller assembly to reengage on forward print media movement to reestablish tension in the printing station.

Abstract: A trench capacitor (10) has a center portion (26) formed from the substrate (14) by a tubular trench (24). A conducting layer (32) is deposed within the tubular trench (24) and is separated from the substrate (14) and center portion (26) by a dielectric layer (30). Since the charge storage area and the trench capacitor (10) includes both the inside and outside of the trench (24), a greater surface area is obtained, thereby increasing the capacitance of the device. A memory cell (34) may be implemented using the capacitor (10).

Abstract: Solar cells formed of semiconductor discrete spheres of P-type interior having an N-type skin are disclosed. The semiconductor spheres are pressed between a pair of aluminum foil members. A plurality of metal pads are formed to the P-type material of the discrete spheres to provide electrical contacts. The aluminum foils are flexible and electrically insulated from one another. One of the foils is electrically connected to the N-type skin of the discrete semiconductor sphere, and the other is electrically connected to the P-type interior of the sphere by means of the metal pads. The cells are patterned in a foil matrix forming an array. Multiple arrays can be interconnected to form a module of solar cell elements for converting sun light into electricity.

Abstract: An EEPROM circuit having a word-erase capability is disclosed using buried bit line fabrication techniques. The word-erasable EEPROM uses minimum additional chip area and minimum fabrication process modification.

Abstract: A linear spatial light modulator with two offset rows of pixels for slight overlap of images, and a printer system using such a spatial light modulator with dark field projection optics is disclosed. The pixels include electrostatically deflectable elements which all bend in the same direction to permit use of dark field projection. The addressing electrodes for the elements are beneath the reflecting surface and arranged perpendicular to the rows of pixels with half on each side of the rows. The printer uses a xerographic engine for conversion of modulated light into print, and an entire row is printed without any scanning.

Abstract: A three step annealing treatment for Hg.sub.1-x Cd.sub.x Te includes a high temperature anneal to reduce excess tellurium, followed by an intermediate temperature anneal to reduce the supersaturation of metal vacancies, and lastly a low temperature anneal to reduce metal vacancies; see FIG. 4. The intermediate anneal reduces the metal vacancy concentration sufficiently that microvoids do not form from condensation of metal vacancies in desired portions of the Hg.sub.1-x Cd.sub.x Te during the low temperature anneal. Alternate preferred embodiments include more than three steps and incremental cooling.

Abstract: A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).

Abstract: The disclosure relates to a circuit to reduce the gate loss in a semiconductor travelling wave power amplifier using series capacitors on the gate feeding lines for a distributed amplifier design. The circuit arrangement significantly increases the gate width of the amplifier with a resultant increases of the broadband output power and efficiency.