Abstract: A method for improving the load time of code and data descriptors is provided. The invention utilizes hardware validation logic for code and data descriptors, but uses a software program to validate system descriptors. In those instances where the descriptor being loaded is a code or data descriptor, system validation checks are not performed. This allows code and data descriptors to be validated and stored into a segment register much faster than if system validation checks were also performed. If the descriptor is found invalid by the hardware validation logic, a branch is made to a software program which is used to determine whether the descriptor is invalid, or is actually a system descriptor. If it is a system descriptor, then system descriptor validation checks are performed by a software program.

Abstract: A method for improving the load time of code and data descriptors is provided. The invention utilizes hardware validation logic for code and data descriptors, but uses a software program to validate system descriptors. In those instances where the descriptor being loaded is a code or data descriptor, system validation checks are not performed. This allows code and data descriptors to be validated during the write back stage of the descriptor store operation, thereby eliminating processing delays typically associated with performing validation. If the descriptor is found invalid by the hardware validation logic, a branch is made to a software program which is used to determine whether the descriptor is invalid, or is actually a system descriptor. If it is a system descriptor, then system descriptor validation checks are performed by a software program.

Abstract: An apparatus and method for improving the execution speed of particular micro instruction sequences is provided, and which allows for exception handling of the micro instruction sequences, as needed. During execution of a micro instruction sequence, particular registers are allowed to be overwritten prior to completion of the entire micro instruction sequence. A tracking mechanism is provided which tracks which registers are overwritten, and restoration logic is provided which stores the "old" contents of the particular registers. If the micro instruction sequence cannot complete, due to a fault, for example, the tracking mechanism indicates which registers have been overwritten, and the restoration logic provides the "old" values to be restored.

Abstract: An apparatus and method for organizing a data array within a cache system to store a plurality of physical pages of data. A single data array is associated with a plurality of tag arrays, each tag array tracking a page size portion of the data array. Indexing into each of the tag arrays is accomplished using the page index from either of the virtual address or the physical address. In addition, selection of indexed tags from the tag arrays is performed by array selection logic which utilizes portions of either of the virtual page number or the physical page number.

Abstract: An apparatus and method which provides specified hold times for communication signals transmitted from a processing device that is capable of operating at different frequencies, to external devices, is provided. The apparatus includes a clock multiplier which generates an internal clock signal which is a multiple of an external clock, a ring oscillator, which provides a number of outputs of the same frequency as the internal clock, but at fixed phase offsets from the internal clock, and clock select circuitry, which selects one of the outputs from the ring oscillator, depending on the speed of the internal clock, to be used as a drive clock signal for a bus unit. Selection of one of the phase offset outputs provides for a specified hold time regardless of the internal clock speed of the processing device.

Abstract: An apparatus for measuring warp of a semiconductor wafer cassette is provided. A wafer cassette is secured within a housing that places the end wall of the cassette in a predetermined position. An array of laser diodes is arranged to transmit a light reference across the end wall of the cassette. An array of photo detectors is placed opposite the laser diodes to detect the transmitted light reference. If the end wall of the cassette is not warped, the transmitted light is blocked by the cassette. If the end wall of the cassette is warped, some or all of the photo detectors receive the transmitted light. Measurement of the light received by the photo detectors is used to determine the nature and degree of warp on the end wall of the cassette.

Abstract: An apparatus for storing selectors directly into segment registers within a single processor cycle. New selectors are stored into addressable segment registers prior to being validated. Old selectors which are shifted into temporary register space prior to being overwritten. If a selector fails validation tests, and requires restoration, the old selector is shifted back into the appropriate segment register thereby restoring the state of the selector.

Abstract: An apparatus for locating exception correction routines within a control ROM of a microprocessor. A control ROM generates micro instructions that are addressable by a microprocessor. A translator generates micro instructions that do not have addresses which may be referenced. Error correction routines must be provided for micro instructions whether they are provided by a translator, or by a control ROM. Exception correction routines are stored in a control ROM at fixed offsets relative to the micro instructions for which they provide correction. For translator generated micro instructions, an address corresponding to an appropriate exception correction routine is provided to the control ROM and latched. This address may later be read from the latch should an exception condition occur.

Abstract: An apparatus and method for handling exceptions during execution of string instructions is provided. The apparatus includes translate/decode logic which repetitively generates a micro instruction sequence applicable to the particular string operation, and an execution unit for executing the micro instruction sequence. A counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is incremented/decremented each time the sequence is executed. The translate/decode logic continues to generate the micro instruction sequence until receiving a signal from the counter which indicates that all of the string has been operated upon, e.g., if the counter reaches zero.

Abstract: A method and apparatus for tracking the fill status of subcache line locations during a cache line fill operation is provided. The tracking system monitors the data cycles of a burst read during a cache line fill, and sets indicators pertaining to which of the sub cache lines within the cache line have been filled. Cache control utilizes the indicators to make those sub cache lines that have been filled available to a processing system as they are filled, rather than waiting for the entire cache line to be filled. Data is stored directly into sub cache line locations without requiring a cache line buffer.

Abstract: An apparatus and method for handling exceptions during execution of string instructions is provided. The apparatus includes a translator which repetitively generates a micro instruction sequence applicable to the particular string operation, and an execution unit for executing the micro instruction sequence. A counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is incremented/decremented each time the sequence is executed. The translator continues to generate the micro instruction sequence until receiving a signal from the counter which indicates that all of the string has been operated upon, e.g., if the counter reaches zero.

Abstract: An apparatus and method for improving the execution of string instructions is provided. The apparatus includes a translator which repetitively generates a micro instruction sequence applicable to the particular string operation to be performed, and an execution unit for executing the micro instruction sequence. In addition, a counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is decremented each time the sequence is executed. The translator continues to generate the micro instruction sequence until receiving a signal from a counter which indicates that all of the string has been operated upon. In addition, the execution unit receives the signal from the counter and tests subsequent micro instructions to determine whether they are associated with string instructions. If so, the execution unit performs NOPs in place of those micro instructions.

Abstract: An apparatus and method for improving the execution speed of register generic micro instructions within a pipeline microprocessor is provided. The microprocessor includes descriptor compare logic which monitors references to last used segment registers, and maintains the base address of the last used segment. As holes are created by later register generic micro instructions, the descriptor compare logic compares operands with that of the last accessed segment register. When an operand of the present micro instruction is the same as the last accessed segment register, the descriptor compare logic provides a pipeline release signal which releases the base address associated with the last accessed segment register directly to the following stage in the pipeline, thereby effectively eliminating the register stage of the pipeline, and the associated hole in the pipeline, for the present micro instruction.

Abstract: A combined removable hard disk drive and removable memory card mechanical lock which provides a portable computer user with an easy and cost effective arrangement to lock inside the computer expensive modular components such as a hard disk drive and memory cards. When installed on a portable computer, the combined lock will prevent the removable hard disk drive and removable memory cards from being removed from the portable computer.

Abstract: A fast fill method and apparatus for an instruction queue within a pipeline processor is provided. An instruction queue is placed between a translator and an instruction register within a pipeline processor to reduce holes or bubbles in the pipeline resulting from either the fetch stage or the translate/decode stage. The instruction queue is fast filled by the translator by providing multiple micro instructions from the translator, in parallel to either or both of the instruction queue and the instruction register. Queue store control logic is provided to manage sequencing of micro instructions between the translator, the instruction queue, and the instruction register.

Abstract: A system is described for selectively configuring a backplane-based SCSI subsystem in at least two alternative drive configurations. A concatenator/splitter (C/S) device enables a user to concatenate several SCSI devices onto a single bus, or alternatively to split the devices onto multiple buses. In either configuration, the bus or buses are properly terminated. The C/S device is located on the backplane between two buses and is connected to each bus by a connector section. A removable interface module plugs into the connector section in either an upright or upside-down orientation, as selected by the user, to choose either a concatenated or split bus configuration. A terminating network is included in the interface module in order to terminate the first bus when the subsystem is configured in the split bus arrangement.

Abstract: A computer is provided with a pair of internal PCMCIA card connection chambers opening outwardly through a pair of housing side wall slots through which PCMCIA cards may be inserted into and withdrawn from the chambers. To facilitate the disconnection and withdrawal of the inserted cards each chamber is provided with a mechanically leveraged card ejector mechanism positioned within a thin space between the facing sides of the inserted card and a housing wall portion of the chamber, and disposed essentially entirely within the peripheral footprint of the inserted card. Each ejector mechanism includes a manually operable actuating plate slidably disposed on the outer side of the computer housing, a card receiving/ejection plate overlying the actuating plate within the housing, and a lever plate sandwiched between the actuating plate and receiving/ejection plate and pivotally connected to the housing.

Abstract: An interface for providing an electrical and mechanical connection of a data processing unit to a data communications card. The connections have a plurality of sockets in a predetermined alignment. Contained within the unit is a series of connectors in an alignment corresponding to the predetermined alignment of the sockets so that when the sockets and the connectors respectively engage, predetermined electrical circuits are completed. An actuator is also disposed within the housing for generating an output signal indicative of the orientation of either the sockets or the connectors. A multiplexer circuit is provided to reverse either the sockets or the connectors, when necessary, in response to the output of the actuator.

Abstract: A rework process for ball grid array (BGA) packages which allows for reuse of devices that have been removed for lack of integrity of solder interconnections. The process uses a rework tool which comprises a plate including one or more depressions corresponding to the contours of inverted BGA packages. A BGA package to be reworked is placed in a respective depression with what remains of the original solder ball grid facing upward. The residual solder balls are wicked away, thus leaving the BGA package with the pads that the solder balls were attached to being exposed. A stencil with BGA patterns punched into it is then placed over the rework tool and solder paste is screened onto the rework tool so that the solder is deposited on the BGA pads via the openings in the stencil. The entire fixture is then subjected to a reflow process to cause the solder to ball up during this process.

Abstract: A system for accurately predicting impending battery failure in battery powered electronic and electrical devices. The system continually monitors changes in battery voltage responsive to load changes and calculates a ratio of the change in voltage to the change in load. When the ratio exceeds a certain threshold value, indicating that the impedance of the battery has risen to near its final value, a user warning indication is generated.