Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a static branch predictor, a prediction correlator, and branch history update logic. If a branch instruction is known to exhibit a bias toward a particular outcome, then the static branch predictor directs the microprocessor, via a precedence signal, to take the particular outcome, regardless of what a dynamic branch prediction for the branch instruction may indicate. Thus, the predicted outcome takes precedence over the dynamic branch prediction for a biased outcome branch instruction. The branch history update logic updates a branch history entry corresponding to a branch instruction following its resolution, unless the precedence signal indicates that a particular outcome for the branch instruction was directed by the static branch predictor. In this case the corresponding branch history entry is not updated.

Abstract: An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program by inserting the test parameters in place of a plurality of non-specific test operands. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

Abstract: An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources.

Abstract: An apparatus is presented for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration. Bus efficiency is improved by providing an apparatus for controlling a read-modify-write transaction to an address in a bus slave device that does not suspend essential features of the system bus during the transaction, namely, pipelining and transaction splitting. The apparatus includes transaction control logic in a bus master device and transaction response logic in a bus slave device. The transaction control logic provides a write barrier command from the bus master device over the on-chip system bus to the bus slave device. The transaction response logic receives the write barrier command, and precludes execution of future transactions to the address within the bus slave device until completion of the read-modify-write transaction while allowing execution of transactions to other addresses within the bus slave device to complete.

Abstract: A covert surveillance system for viewing images from a remote location is provided. The surveillance system provides a mirror, lens and camera arrangement within a small enclosure that allows full 360 degree pan, tilt, zoom, focus and iris control from a remote location. The system receives control commands such as rotate left, zoom out and tilt down via a radio receiver, and controls the camera accordingly. Images viewed by the camera are transmitted to a remote receiver for display on a monitor, or for recording. Continuous camera rotation is achieved by use of a specialized conductive drum that provides continuous electrical contact between camera signals and camera control. In one embodiment, the surveillance system is mounted in place of a photo detector in a street lamp, making the camera virtually undetectable. In addition, a rotatable directional antenna is included in the surveillance system to allow surveillance at great distances from the system.

Abstract: An apparatus and method are provided that enable T1 (or E1) telecommunications frames to be transmitted between T1 (or E1) telecommunications switches over a high bandwidth packet-switched network. The apparatus includes trunk interface logic and network translation logic. The trunk interface logic is coupled a central office switch via a central office switch trunk, and receives the telecommunications frames from the central office switch. The network translation logic is coupled to the trunk interface logic. The network translation logic translates the telecommunications frames into network packets that the telecommunications frame data may be transferred over the high bandwidth packet-switched network.

Abstract: In a computer having a single execution pipeline, the invention provides a method for executing paired MMX-type instructions. The method includes executing two MMX-type instructions as paired MMX instructions. If execution of the paired MMX instructions causes an exception, pairing of instructions is disabled, and the two MMX-type instructions are re-executed in sequential fashion. Paired execution is re-enabled following re-execution of the two MMX-type instructions.

Abstract: An apparatus and method for tracking the LRU state of memory locations in data ways or nodes is provided. Vectors are utilized between each entry in each node with the direction of the vectors corresponding to the LRU state of an entry. The vectors are stored within a vector table. Vector r/w control is provided to update only those vectors corresponding to entries that are being accessed, with the update occurring without regard to the LRU state of entries that are not being accessed. A vector mask is coupled between the vector r/w control and the vector table to prevent update of vectors corresponding to entries that are not being accessed. When an entry (such as a cache line in a set associative cache) within the node is accessed, the vectors associated with the node are updated to reflect the access, with no need to determine the LRU state of other nodes.

Abstract: An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing-that are not significantly impacted by the number of stages in the microprocessor's pipeline. The present invention provides a cache for storage of multiple intermediate address operands. The cache is accessed by an address-dependent micro instruction to retrieve a required address operand. The apparatus includes an update forwarding cache, address update logic, and address operand configuration logic. The update forwarding cache stores the intermediate address operands. The address update logic receives the intermediate address operands as they are generated and enters the intermediate address operands into the update forwarding cache. The address operand configuration logic accesses the intermediate address operands to configure and provide an address operand that is required an address-dependent micro instruction.

Abstract: An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing—that are not significantly impacted by the number of stages in the microprocessor's pipeline. In contrast to conventional result distribution schemes where an intermediate result is distributed to multiple pipeline stages, the present invention provides a cache for storage of multiple intermediate results. The cache is accessed by a dependent micro instruction to retrieve required operands. The apparatus includes a result forwarding cache, result update logic, and operand configuration logic. The result forwarding cache stores the intermediate results. The result update logic receives the intermediate results as they are generated and enters the intermediate results into the result forwarding cache.

Abstract: A CMOS slew-controlled split-voltage output driver is provided whose I/O logic is supplied at one (higher) voltage level and whose computational logic is supplied at a second (lower) voltage level. The slew-controlled split-voltage output driver includes an output driver circuit, a driver control circuit, and a feedback-enhanced level translator circuit. The output driver circuit drives the output signal to a low level, a high level, or a tri-state level. The driver control circuit receives an enable signal, and employs the enable signal to control turn on and turn off of the N-channel sink transistor. The feedback-enhanced level translator circuit receives an output state signal whose highlevel state is essentially equal to a second power supply voltage. The feedback-enhanced level translator circuit generates the enable signal to the level essentially equal to the first power supply voltage, and isolates generation of the enable signal from operation of the driver control circuit.

Abstract: An improved Agree branch predictor is provided. The branch predictor biasing bit is generated by a static predictor that makes a static prediction. The static predictor maintains a register storing an instruction preceding a conditional branch instruction for which the prediction is to be made. The static predictor makes the static prediction based upon a table of predetermined combinations of the preceding instruction type and upon a test type specifying a condition upon which the conditional branch instruction will be taken. In addition, the static predictor makes the static prediction based upon the sign of a displacement for calculating a target address of the branch. The static prediction is correlated with an Agree/Disagree prediction generated by a history table of previous outcomes of conditional branch instructions.

Abstract: A method and a system is disclosed that provide means to enable individuals with speech, language and reading based communication disabilities, due to a temporal processing problem, to improve their temporal processing abilities as well as their communication abilities. The method and system include provisions to elongate portions of phonemes that have brief and/or rapidly changing acoustic spectra, such as occur in the stop consonants b and d in-the phonemes /ba/ and /da/, as well as reduce the duration of the steady state portion of the syllable. In addition, some emphasis is added to the rapidly changing segments of these phonemes. Additionally, the disclosure includes method for and computer software to modify fluent speech to make the modified speech better recognizable by communicatively impaired individuals. Finally, the disclosure includes method for and computer software to train temporal processing abilities, specifically speed and precision of temporal integration, sequencing and serial memory.

Abstract: A method and a system is disclosed that provide means to enable individuals with speech, language and reading based communication disabilities, due to a temporal processing problem, to improve their temporal processing abilities as well as their communication abilities. The method and system include provisions to elongate portions of phonemes that have brief and/or rapidly changing acoustic spectra, such as occur in the stop consonants b and d in the phonemes /ba/ and /da/, as well as reduce the duration of the steady state portion of the syllable. In addition, some emphasis is added to the rapidly changing segments of these phonemes. Additionally, the disclosure includes method for and computer software to modify fluent speech to make the modified speech better recognizable by communicatively impaired individuals. Finally, the disclosure includes method for and computer software to train temporal processing abilities, specifically speed and precision of temporal integration, sequencing and serial memory.

Abstract: A method and a system is disclosed that provide means to enable individuals with speech, language and reading based communication disabilities, due to a temporal processing problem, to improve their temporal processing abilities as well as their communication abilities. The method and system include provisions to elongate portions of phonemes that have brief and/or rapidly changing acoustic spectra, such as occur in the stop consonants b and d in the phonemes /ba/ and /da/, as well as reduce the duration of the steady state portion of the syllable. In addition, some emphasis is added to the rapidly changing segments of these phonemes. Additionally, the disclosure includes method for and computer software to modify fluent speech to make the modified speech better recognizable by communicatively impaired individuals. Finally, the disclosure includes method for and computer software to train temporal processing abilities, specifically speed and precision of temporal integration, sequencing and serial memory.

Abstract: A method and a system is disclosed that provide means to enable individuals with speech, language and reading based communication disabilities, due to a temporal processing problem, to improve their temporal processing abilities as well as their communication abilities. The method and system include provisions to elongate portions of phonemes that have brief and/or rapidly changing acoustic spectra, such as occur in the stop consonants b and d in the phonemes /ba/ and /da/, as well as reduce the duration of the steady state portion of the syllable. In addition, some emphasis is added to the rapidly changing segments of these phonemes. Additionally, the disclosure includes method for and computer software to modify fluent speech to make the modified speech better recognizable by communicatively impaired individuals. Finally, the disclosure includes method for and computer software to train temporal processing abilities, specifically speed and precision of temporal integration, sequencing and serial memory.

Abstract: A method and a system is disclosed that provide means to enable individuals with speech, language and reading based communication disabilities, due to a temporal processing problem, to improve their temporal processing abilities as well as their communication abilities. The method and system include provisions to elongate portions of phonemes that have brief and/or rapidly changing acoustic spectra, such as occur in the stop consonants b and d in the phonemes /ba/ and /da/, as well as reduce the duration of the steady state portion of the syllable. In addition, some emphasis is added to the rapidly changing segments of these phonemes. Additionally, the disclosure includes method for and computer software to modify fluent speech to make the modified speech better recognizable by communicatively impaired individuals. Finally, the disclosure includes method for and computer software to train temporal processing abilities, specifically speed and precision of temporal integration, sequencing and serial memory.

Abstract: A method and a system is disclosed that provide means to enable individuals with speech, language and reading based communication disabilities, due to a temporal processing problem, to improve their temporal processing abilities as well as their communication abilities. The method and system include provisions to elongate portions of phonemes that have brief and/or rapidly changing acoustic spectra, such as occur in the stop consonants b and d in the phonemes /ba/ and /da/, as well as reduce the duration of the steady state portion of the syllable. In addition, some emphasis is added to the rapidly changing segments of these phonemes. Additionally, the disclosure includes method for and computer software to modify fluent speech to make the modified speech better recognizable by communicatively impaired individuals. Finally, the disclosure includes method for and computer software to train temporal processing abilities, specifically speed and precision of temporal integration, sequencing and serial memory.

Abstract: A method and a system is disclosed that provide means to enable individuals with speech, language and reading based communication disabilities, due to a temporal processing problem, to improve their temporal processing abilities as well as their communication abilities. The method and system include provisions to elongate portions of phonemes that have brief and/or rapidly changing acoustic spectra, such as occur in the stop consonants b and d in the phonemes /ba/ and /da/, as well as reduce the duration of the steady state portion of the syllable. In addition, some emphasis is added to the rapidly changing segments of these phonemes. Additionally, the disclosure includes method for and computer software to modify fluent speech to make the modified speech better recognizable by communicatively impaired individuals. Finally, the disclosure includes method for and computer software to train temporal processing abilities, specifically speed and precision of temporal integration, sequencing and serial memory.

Abstract: A portion of an x86 microprocessor that supports MMX instructions provides a write tracking unit that tracks writes to a separately provided MMX register file, and updates a status register accordingly. A write control unit uses the contents of the status register to control transfers between the MMX register file and the FP register file, so as to only copy those registers that have changed. According to another aspect of the invention, the write control unit insures that architecturally required modifications to the exponent portion of FP registers corresponding to modified MMX registers are provided.