Abstract: An apparatus and method for performing a floating point multiply (by a fixed graphics constant), and converting the product of the multiply into an integer, within a single operation is provided. The apparatus includes detection logic to determine whether a special multiply/convert operation is specified, and if so, floating point conversion logic to adjust a bias constant prior to conversion of the floating point number to an integer. More specifically, if the multiply/convert operation specified relates to calculation of graphic points for display, execution of the multiply convert operation effectively multiplies a specified floating point number by a graphics constant, as part of subtracting the exponent bias.

Abstract: An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

Abstract: An apparatus and method for screening an individual's ability to process acoustic events is provided. The invention provides sequences (or trials) of acoustically processed target and distractor phonemes to a subject for identification. The acoustic processing includes amplitude emphasis of selected frequency envelopes, stretching (in the time domain) of selected portions of phonemes, and phase adjustment of selection portions of phonemes relative to a base frequency. After a number of trials, the method of the present invention develops a profile for an individual that indicates whether the individual's ability to process acoustic events is within a normal range, and if not, what processing can provide the individual with optimal hearing. The individual's profile can then be used by a listening or processing device to particularly emphasize, stretch, or otherwise manipulate an audio stream to provide the individual with an optimal chance of distinguishing between similar acoustic events.

Abstract: A reclining chair having a base frame (1) supporting a reclining unit (2) by a mechanism having downwardly converging swing links (15 and 16) pivoted at their upper ends at (22 and 23) respectively to the frame, a rigid member (14) pivotally connected to the lower ends of the swing links (15 and 16 at 20 and 21). The rigid member (14) has a link (13) rigidly connected to it which in turn is rigidly connected to the reclining unit (2). The center of gravity of the reclining unit with its occupant is maintained in a substantially horizontal plane as the unit moves from upright to reclined positions.

Abstract: An apparatus and method for training the sensory perceptual system in a language learning impaired (LLI) subject is provided. The apparatus and method incorporates a number of different programs to be played by the subject. The programs artificially process selected portions of language elements, called phonemes, so they will be more easily distinguished by an LLI subject, and gradually improves the subject's neurological processing of the elements through repetitive stimulation. The programs continually monitor a subject's ability to distinguish the processed language elements, and adaptively configures the programs to challenge and reward the subject by altering the degree of processing. Through adaptive control and repetition of processed speech elements, and presentation of the speech elements in a creative fashion, a subject's temporal processing of acoustic events common to speech are significantly improved.

Abstract: An apparatus and method for improving the execution speed of stack segment load operations is provided. Rather than delaying translation of instructions following stack segment loads, until the load is complete, the present invention presumes that no change will be made to the stack address size. Tracking of the stack address size, at the time of translation, is performed by a plurality of SAS bits associated with translated micro instructions, and logic is provided which compares the tracked SAS bits with any change in the stack address size. If no change is made by the stack load operation, the already translated instructions execute immediately. If a change is made by the stack load operation, logic interrupts processing of the translated instructions, and the instructions are retranslated using the new stack address size.

Abstract: An apparatus and method for recording a floating point macro instruction error pointer within a microprocessor is provided. The apparatus includes translation/control logic for generating a micro instruction sequence to perform a floating point operation. The micro instruction sequence includes a first micro instruction, inserted in the sequence in place of a translate slip, which directs the microprocessor to store a first part of the floating point macro instruction error pointer associated with a floating point macro instruction. The micro instruction sequence also includes a micro instruction extension, associated with a floating point micro instruction within the sequence. The extension directs the microprocessor to store a second part of the floating point macro instruction error pointer. The error pointer is stored in zero effective time increments without requiring additional hardware.

Abstract: A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and provides a signal indicating the dependency. The microprocessor also has interlock logic that, in the event of a dependency forwards a new target location to the preceding floating point micro instruction. The microprocessor also includes target location modification logic that receives the new target location and for provides the new target location to the preceding floating point micro instruction. Modification of the target location allows the floating point exchange micro instruction sequence to execute without resolution delay.

Abstract: An apparatus and method for loading aligned/misaligned data from a cache within a microprocessor is provided. The apparatus contains a first ALU for generating a partial offset, alignment check logic for quickly estimating the alignment of the data, a second ALU for generating a linear address, and alignment confirmation logic for confirming the alignment of the data. Quick estimation of data alignment allows the load of data to proceed before full alignment calculations are completed. A mandatory slip during data alignment checking is eliminated.

Abstract: An apparatus and method for improving the execution speed of macro instructions which have an operand located in memory, and where the destination of the result is in memory. The apparatus includes an ALU Store which monitors micro instructions generated by a translator. When a macro instruction is fetched which has an operand located in memory, and the result is to be stored in the same location in memory, the translator generates a LOAD micro instruction followed immediately by an operation micro instruction which contains STORE indicia, such as a STORE suffix. The ALU Store latches the address created by the LOAD micro instruction, and uses this latched address in the following operation store micro instruction.

Abstract: An apparatus and method for training the sensory perceptual system in a language learning impaired (LLI) subject is provided. The apparatus and method incorporates a number of different programs to be played by the subject. The programs artificially process selected portions of language elements, called phonemes, so they will be more easily distinguished by an LLI subject, and gradually improves the subject's neurological processing of the elements through repetitive stimulation. The programs continually monitor a subject's ability to distinguish the processed language elements, and adaptively configures the programs to challenge and reward the subject by altering the degree of processing. Through adaptive control and repetition of processed speech elements, and presentation of the speech elements in a creative fashion, a subject's temporal processing of acoustic events common to speech are significantly improved.

Abstract: An apparatus and method for sharing cache lines within a split data/code cache is provided. The invention utilizes cache snoop and state control, coupled to both a data cache and a code cache, which allows the data cache to snoop fetches to the code cache, and allows the code cache to snoop reads and writes to the data cache. In addition, cache snoop and state control modifies the state of a particular cache line within both of the caches according to the MESI cache coherency protocol to allow a single cache line to reside in both the data cache, and the code cache, in a Shared state. The invention allows the shared cache line to be fetched from the code cache, and retrieved from the data cache, until it is overwritten or modified in the data cache. In one embodiment, an instance of a cache line within either the code or data cache can be snarfed into the other cache, and marked as shared.

Abstract: A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.

Abstract: An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and logically merges the fuse states with a default configuration for the functional blocks. The result of the merge operation is stored in a feature control register that individually enables/disables the functional blocks. The control unit also receives a write command from an external source that modifies the feature control register, after the device is shipped from the manufacturer. The control unit selectively blocks writes to the feature control register that attempt to enable/disable functional blocks that should not modified.

Abstract: A covert surveillance system for viewing images from a remote location is provided. The surveillance system provides a mirror, lens and camera arrangement within a small enclosure which allows full 360 degree pan, tilt, zoom, focus and iris control from a remote location. The system receives control commands such as rotate left, zoom out and tilt down via a radio receiver, and controls the camera accordingly. Images viewed by the camera are transmitted to a remote receiver for display on a monitor, or for recording. Continuous camera rotation is achieved by use of a specialized conductive drum which provides continuous electrical contact between camera signals and camera control. In one embodiment, the surveillance system is mounted in place of a photo detector in a street lamp, making the camera virtually undetectable.

Abstract: A method and apparatus for handling interrupts after transition of a mask flag is provided. In x86 processors, if the IF flag is set, interrupts are to be handled. However, if the IF flag transitions from a clear state to a set state, and the instruction which sets the IF bit is an STI instruction, then a pending interrupt is to be delayed for one instruction, unless the following instruction is a floating point instruction, and then the interrupt is to be handled immediately. The invention allows an interrupt to cause a branch to an exception handler if the IF bit is set. The exception handler determines whether the prior instruction was an STI instruction, and whether the prior state of the IF bit was clear. If both these conditions are true, the exception handler branches back to the main program. If either condition is not true, the exception handler branches to an interrupt service routine.

Abstract: An apparatus and method for improving the execution speed of programs including register generic micro instructions within a pipeline processor is provided. The processor contains a translator and a control ROM, both of which may produce micro instructions associated with the program. When a micro instruction is produced by the control ROM, and when the micro instruction contains register generic operands, the micro instruction is placed within a ROM instruction queue. While in the instruction queue, register specific operands may be placed within the micro instruction. Thus, by the time the micro instruction reaches an instruction register, the micro instruction is ready for execution by later stages in the pipeline, without requiring a hole or delay in the pipeline to fill in register specific operands.

Abstract: A method and apparatus for handling interrupts after transition of a mask flag is provided. In x86 processors, if the IF flag is cleared, interrupts are to be masked. If the IF flag is set, interrupts are to be handled. However, if the IF flag transitions from a clear state to a set state, and the instruction which sets the IF bit is an STI instruction, then a pending interrupt is to be delayed for one instruction, unless the following instruction is a floating point instruction, and then the interrupt is to be handled immediately. The invention allows an interrupt to cause a branch to an exception handler if the IF bit is set. The exception handler determines whether the prior instruction was an STI instruction, and whether the prior state of the IF bit was clear. If both these conditions are true, the exception handler branches back to the main program. If either condition is not true, the exception handler branches to an interrupt service routine.

Abstract: A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/column select switches. Temporary enabling of redundant rows/columns allows testing of redundancy prior to alteration of the permanent switch logic. The control unit, upon command from a wafer tester, selectively enables particular redundant rows/columns to allow those redundant rows/columns to be tested. After testing, if the redundant rows/columns repair memory defects, permanent switch logic may be altered, without requiring further testing of the redundant circuitry.

Abstract: A method and apparatus for tracking the fill status of sub cache line locations during a cache line fill operation is provided. The tracking system monitors the data cycles of a burst read during a cache line fill, and sets indicators pertaining to which of the sub cache lines within the cache line have been filled. Cache control utilizes the indicators to make those sub cache lines that have been filled available to a processing system as they are filled, rather than waiting for the entire cache line to be filled. Data is stored directly into sub cache line locations without requiring a cache line buffer.